0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits

S. O'uchi; K. Endo; Y. X. Liu; T. Nakagawa; T. Matsukawa; Y. Ishikawa; J. Tsukada; H. Yamauchi; T. Sekigawa; H. Koike; K. Sakamoto; M. Masahara

doi:10.1109/ESSCIRC.2010.5619746

0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits

S. O'uchi, K. Endo, Y. X. Liu, T. Nakagawa, T. Matsukawa, Y. Ishikawa, J. Tsukada, H. Yamauchi, T. Sekigawa, H. Koike, K. Sakamoto, M. Masahara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast but without static noise margin (SNM) and those too slow but with too much SNM are salvaged. Thus, this dynamic PG control greatly improves the variation tolerance of 6-Tr FinFET SRAM. The experimental and simulation results suggest that this technique will enable 0.5V operation at read delay within 2ns in an L_g-20nm low-standby-power (LSTP) technology.

Original language	English
Title of host publication	ESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages	474-477
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2010.5619746
Publication status	Published - 2010 Dec 27
Externally published	Yes
Event	36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain Duration: 2010 Sept 14 → 2010 Sept 16

Publication series

Name	ESSCIRC 2010 - 36th European Solid State Circuits Conference

Other

Other	36th European Solid State Circuits Conference, ESSCIRC 2010
Country/Territory	Spain
City	Sevilla
Period	10/9/14 → 10/9/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2010.5619746

Cite this

O'uchi, S., Endo, K., Liu, Y. X., Nakagawa, T., Matsukawa, T., Ishikawa, Y., Tsukada, J., Yamauchi, H., Sekigawa, T., Koike, H., Sakamoto, K., & Masahara, M. (2010). 0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. In ESSCIRC 2010 - 36th European Solid State Circuits Conference (pp. 474-477). [5619746] (ESSCIRC 2010 - 36th European Solid State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2010.5619746

0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. / O'uchi, S.; Endo, K.; Liu, Y. X. et al.

ESSCIRC 2010 - 36th European Solid State Circuits Conference. 2010. p. 474-477 5619746 (ESSCIRC 2010 - 36th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

O'uchi, S, Endo, K, Liu, YX, Nakagawa, T, Matsukawa, T, Ishikawa, Y, Tsukada, J, Yamauchi, H, Sekigawa, T, Koike, H, Sakamoto, K & Masahara, M 2010, 0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. in ESSCIRC 2010 - 36th European Solid State Circuits Conference., 5619746, ESSCIRC 2010 - 36th European Solid State Circuits Conference, pp. 474-477, 36th European Solid State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, 10/9/14. https://doi.org/10.1109/ESSCIRC.2010.5619746

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title = "0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits",

abstract = "This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast but without static noise margin (SNM) and those too slow but with too much SNM are salvaged. Thus, this dynamic PG control greatly improves the variation tolerance of 6-Tr FinFET SRAM. The experimental and simulation results suggest that this technique will enable 0.5V operation at read delay within 2ns in an Lg-20nm low-standby-power (LSTP) technology.",

author = "S. O'uchi and K. Endo and Liu, {Y. X.} and T. Nakagawa and T. Matsukawa and Y. Ishikawa and J. Tsukada and H. Yamauchi and T. Sekigawa and H. Koike and K. Sakamoto and M. Masahara",

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doi = "10.1109/ESSCIRC.2010.5619746",

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T1 - 0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits

AU - O'uchi, S.

AU - Endo, K.

AU - Liu, Y. X.

AU - Nakagawa, T.

AU - Matsukawa, T.

AU - Ishikawa, Y.

AU - Tsukada, J.

AU - Yamauchi, H.

AU - Sekigawa, T.

AU - Koike, H.

AU - Sakamoto, K.

AU - Masahara, M.

PY - 2010/12/27

Y1 - 2010/12/27

N2 - This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast but without static noise margin (SNM) and those too slow but with too much SNM are salvaged. Thus, this dynamic PG control greatly improves the variation tolerance of 6-Tr FinFET SRAM. The experimental and simulation results suggest that this technique will enable 0.5V operation at read delay within 2ns in an Lg-20nm low-standby-power (LSTP) technology.

AB - This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast but without static noise margin (SNM) and those too slow but with too much SNM are salvaged. Thus, this dynamic PG control greatly improves the variation tolerance of 6-Tr FinFET SRAM. The experimental and simulation results suggest that this technique will enable 0.5V operation at read delay within 2ns in an Lg-20nm low-standby-power (LSTP) technology.

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ER -

0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits

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