135 GHz 98mW 10 Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Mizuki Motoyoshi, Naoko Ono, Kosuke Katayama, Kyoya Takano, Minoru Fujishima

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


An amplitude shift keying transmitter and receiver chipset with low power consumption using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multigigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region

Original languageEnglish
Pages (from-to)86-93
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number1
Publication statusPublished - 2014 Jan
Externally publishedYes


  • Ask transceiver
  • Cmos
  • D-band
  • High-speed
  • Shortmillimeter-wave
  • Wireless

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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