135 GHz 98mW 10 Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Mizuki Motoyoshi; Naoko Ono; Kosuke Katayama; Kyoya Takano; Minoru Fujishima

doi:10.1587/transfun.E97.A.86

135 GHz 98mW 10 Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Mizuki Motoyoshi, Naoko Ono, Kosuke Katayama, Kyoya Takano, Minoru Fujishima

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

An amplitude shift keying transmitter and receiver chipset with low power consumption using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multigigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region

Original language	English
Pages (from-to)	86-93
Number of pages	8
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E97-A
Issue number	1
DOIs	https://doi.org/10.1587/transfun.E97.A.86
Publication status	Published - 2014 Jan
Externally published	Yes

Keywords

Ask transceiver
Cmos
D-band
High-speed
Shortmillimeter-wave
Wireless

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1587/transfun.E97.A.86

Cite this

@article{33adfec6316241d2bbe1a101b41038cf,

title = "135 GHz 98mW 10 Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset",

abstract = "An amplitude shift keying transmitter and receiver chipset with low power consumption using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multigigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region",

keywords = "Ask transceiver, Cmos, D-band, High-speed, Shortmillimeter-wave, Wireless",

author = "Mizuki Motoyoshi and Naoko Ono and Kosuke Katayama and Kyoya Takano and Minoru Fujishima",

year = "2014",

month = jan,

doi = "10.1587/transfun.E97.A.86",

language = "English",

volume = "E97-A",

pages = "86--93",

journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",

issn = "0916-8508",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "1",

}

TY - JOUR

T1 - 135 GHz 98mW 10 Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

AU - Motoyoshi, Mizuki

AU - Ono, Naoko

AU - Katayama, Kosuke

AU - Takano, Kyoya

AU - Fujishima, Minoru

PY - 2014/1

Y1 - 2014/1

N2 - An amplitude shift keying transmitter and receiver chipset with low power consumption using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multigigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region

AB - An amplitude shift keying transmitter and receiver chipset with low power consumption using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multigigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region

KW - Ask transceiver

KW - Cmos

KW - D-band

KW - High-speed

KW - Shortmillimeter-wave

KW - Wireless

UR - http://www.scopus.com/inward/record.url?scp=84891768996&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84891768996&partnerID=8YFLogxK

U2 - 10.1587/transfun.E97.A.86

DO - 10.1587/transfun.E97.A.86

M3 - Article

AN - SCOPUS:84891768996

SN - 0916-8508

VL - E97-A

SP - 86

EP - 93

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

IS - 1

ER -

135 GHz 98mW 10 Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset

Abstract

Keywords

ASJC Scopus subject areas

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