TY - GEN
T1 - 1.44F2 memory cell technology with the stacked-surrounding gate transistor (S-SGT) DRAM
AU - Endoh, T.
AU - Sakuraba, H.
AU - Shinmei, K.
AU - Masuoka, F.
PY - 1999
Y1 - 1999
N2 - The proposed Stacked-Surrounding Gate Transistor (S-SGT) DRAM is structured by stacking several SGT-type cells in series vertically. When S-SGT DRAM is stacking 4 cells and one bit-line of both S-SGT and normal DRAM has 1K-bit cells, S-SGT DRAM can realize cell area per bit of 1.44F2, while cell area per bit of normal DRAM with the same design rule is 12F2, and S-SGT DRAM achieves 230% larger the signal capacitance over total bit-line capacitance (Cs/Cb) than that of normal DRAM.
AB - The proposed Stacked-Surrounding Gate Transistor (S-SGT) DRAM is structured by stacking several SGT-type cells in series vertically. When S-SGT DRAM is stacking 4 cells and one bit-line of both S-SGT and normal DRAM has 1K-bit cells, S-SGT DRAM can realize cell area per bit of 1.44F2, while cell area per bit of normal DRAM with the same design rule is 12F2, and S-SGT DRAM achieves 230% larger the signal capacitance over total bit-line capacitance (Cs/Cb) than that of normal DRAM.
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M3 - Conference contribution
AN - SCOPUS:0033298221
SN - 0780352351
SN - 9780780352353
T3 - 2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
SP - 451
EP - 454
BT - 2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings
PB - IEEE
T2 - 22nd International Conference on Microelectronics (MIEL 2000)
Y2 - 14 May 2000 through 17 May 2000
ER -