1.5 V-supply 200 MHz pipelined multiplier using multiple-valued current-mode MOS differential logic circuits

Takahiro Hanyu; Akira Mochizuki; Michitaka Kameyama

1.5 V-supply 200 MHz pipelined multiplier using multiple-valued current-mode MOS differential logic circuits

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

RIEC - Computing System Platforms Division

Tohoku University

Research output: Contribution to journal › Conference article › peer-review

10 Citations (Scopus)

Abstract

The design of a multiple-valued current-mode (MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation is presented. A multiple-valued differential logic circuit (DLC) is used as a basic component to make a signal-voltage swing small yet driving capability large. The use of DLC enables high-speed operations with reduced device and interconnection counts at low power dissipation. The arithmetic circuits show promise as an emerging technology supporting giga-scale integration.

Original language	English
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	38
Publication status	Published - 1995 Feb
Event	Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1995 Feb 15 → 1995 Feb 17

Cite this

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title = "1.5 V-supply 200 MHz pipelined multiplier using multiple-valued current-mode MOS differential logic circuits",

abstract = "The design of a multiple-valued current-mode (MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation is presented. A multiple-valued differential logic circuit (DLC) is used as a basic component to make a signal-voltage swing small yet driving capability large. The use of DLC enables high-speed operations with reduced device and interconnection counts at low power dissipation. The arithmetic circuits show promise as an emerging technology supporting giga-scale integration.",

author = "Takahiro Hanyu and Akira Mochizuki and Michitaka Kameyama",

year = "1995",

month = feb,

language = "English",

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journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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note = "Proceedings of the 1995 IEEE International Solid-State Circuits Conference ; Conference date: 15-02-1995 Through 17-02-1995",

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AU - Hanyu, Takahiro

AU - Mochizuki, Akira

AU - Kameyama, Michitaka

PY - 1995/2

Y1 - 1995/2

N2 - The design of a multiple-valued current-mode (MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation is presented. A multiple-valued differential logic circuit (DLC) is used as a basic component to make a signal-voltage swing small yet driving capability large. The use of DLC enables high-speed operations with reduced device and interconnection counts at low power dissipation. The arithmetic circuits show promise as an emerging technology supporting giga-scale integration.

AB - The design of a multiple-valued current-mode (MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation is presented. A multiple-valued differential logic circuit (DLC) is used as a basic component to make a signal-voltage swing small yet driving capability large. The use of DLC enables high-speed operations with reduced device and interconnection counts at low power dissipation. The arithmetic circuits show promise as an emerging technology supporting giga-scale integration.

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M3 - Conference article

AN - SCOPUS:0029256356

SN - 0193-6530

VL - 38

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Proceedings of the 1995 IEEE International Solid-State Circuits Conference

Y2 - 15 February 1995 through 17 February 1995

ER -

1.5 V-supply 200 MHz pipelined multiplier using multiple-valued current-mode MOS differential logic circuits

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