The design of a multiple-valued current-mode (MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation is presented. A multiple-valued differential logic circuit (DLC) is used as a basic component to make a signal-voltage swing small yet driving capability large. The use of DLC enables high-speed operations with reduced device and interconnection counts at low power dissipation. The arithmetic circuits show promise as an emerging technology supporting giga-scale integration.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 1995 Feb|
|Event||Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA|
Duration: 1995 Feb 15 → 1995 Feb 17