1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

Takashi Ohsawa; H. Koike; S. Miura; H. Honjo; K. Tokutome; S. Ikeda; T. Hanyu; H. Ohno; T. Endoh

doi:10.1109/VLSIC.2012.6243782

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

Takashi Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

58 Citations (Scopus)

Abstract

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under V _dd=1V. The 1Mb chip with 2.19μm ² cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.

Original language	English
Title of host publication	2012 Symposium on VLSI Circuits, VLSIC 2012
Pages	46-47
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2012.6243782
Publication status	Published - 2012 Sept 28
Event	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States Duration: 2012 Jun 13 → 2012 Jun 15

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2012 Symposium on VLSI Circuits, VLSIC 2012
Country/Territory	United States
City	Honolulu, HI
Period	12/6/13 → 12/6/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2012.6243782

Cite this

Ohsawa, T., Koike, H., Miura, S., Honjo, H., Tokutome, K., Ikeda, S., Hanyu, T., Ohno, H., & Endoh, T. (2012). 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. In 2012 Symposium on VLSI Circuits, VLSIC 2012 (pp. 46-47). [6243782] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2012.6243782

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. / Ohsawa, Takashi; Koike, H.; Miura, S. et al.
2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 46-47 6243782 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohsawa, T, Koike, H , Miura, S , Honjo, H, Tokutome, K, Ikeda, S , Hanyu, T , Ohno, H & Endoh, T 2012, 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. in 2012 Symposium on VLSI Circuits, VLSIC 2012., 6243782, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 46-47, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 12/6/13. https://doi.org/10.1109/VLSIC.2012.6243782

Ohsawa T, Koike H , Miura S , Honjo H, Tokutome K, Ikeda S et al. 1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. In 2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 46-47. 6243782. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2012.6243782

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abstract = "A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under V dd=1V. The 1Mb chip with 2.19μm 2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.",

author = "Takashi Ohsawa and H. Koike and S. Miura and H. Honjo and K. Tokutome and S. Ikeda and T. Hanyu and H. Ohno and T. Endoh",

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AU - Miura, S.

AU - Honjo, H.

AU - Tokutome, K.

AU - Ikeda, S.

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AU - Ohno, H.

AU - Endoh, T.

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1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

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