2.4F 2 memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM

Tetsuo Endoh, Masahiko Suzuki, Hiroshi Sakuraba, Fujio Masuoka

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)


This paper proposes 2.4F 2 memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM. One unit of the S-SGT DRAM is formed by stacking several SGT-type cells in series vertically. The SGT-type cell itself arranges gate, source, drain and plate on a silicon pillar vertically. Both gate and plate electrode surround the silicon pillar. Subsequently applied trench etching and sidewall spacer formation during S-SGT DRAM formation causes a step-like silicon pillar structure. Due to these steps, gate, plate and diffusion layer in one S-SGT DRAM unit are fabricated vertically by a self-aligned process. The cell size dependence of the self-aligned-type S-SGT DRAM was analyzed with regard to the above steps widths and the number of cells in one unit. As a result, the cell design for minimizing the cell size of this device has been formulated. By using the proposed cell design, it is demonstrated by process simulation that the S-SGT DRAM in 0.5 μm design rule can achieve a cell size of 2.4F 2, which is half of the cell size of a conventional SGT DRAM cell (4.8F 2). Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs.

Original languageEnglish
Pages (from-to)1599-1603
Number of pages5
JournalIEEE Transactions on Electron Devices
Issue number8
Publication statusPublished - 2001 Aug


  • Cell design
  • DRAM
  • Stacked-surrounding gate transistor (S-SGT)
  • Surrounding gate transistor (SGT)


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