@inproceedings{5915ec13152f42bd84690d9092af2da4,
title = "2Mb SPRAM design: Bi-directional current write and parallelizing-direction current read schemes based on spin-transfer torque switching",
abstract = "A 1.8V 2-Mb SPRAM (SPin-transfer torque RAM) chip using 0.2-μm logic process with MgO tunneling barrier cell demonstrates the circuit technologies for potential low power non-volatile RAM, or universal memory. This chip features: an array scheme with bit-by-bit bi-directional current write to achieve proper spin-transfer torque writing of 100-ns, and parallelizing- direction current reading with low voltage bit-line that leads to 40-ns access time.",
keywords = "Low power RAM, Nonvolatile RAM, Spin-transfer torque, TMR, Universal RAM",
author = "R. Takemura and T. Kawahara and K. Miura and J. Hayakawa and S. Ikeda and Lee, {Y. M.} and R. Sasaki and Y. Goto and K. Ito and T. Meguro and F. Matsukura and H. Takahashi and H. Matsuoka and H. Ohno",
year = "2007",
doi = "10.1109/ICICDT.2007.4299581",
language = "English",
isbn = "1424407567",
series = "Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT",
pages = "238--241",
booktitle = "Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT",
note = "2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT ; Conference date: 30-05-2007 Through 01-06-2007",
}