3D integration technology and reliability challenges

Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of the super-chip are described. In addition, the reliability challenges such as the mechanical stress/strain and Cu contamination are discussed. Cu TSVs with the diameter of 20-μm induced the maximum compressive stress of ∼1 GPa at the Si substrate adjacent to them after annealed at 300°C. Mechanical strain/stress and crystal defects were produced in extremely thin wafer of 10μm thickness not only during the thinning but also after the bonding using fine-pitch, high-density metal bump. The influences of Cu contamination from the back surface of the thinned wafer and Cu TSVs on device reliability were evaluated by C-t analysis. The C-t curves of MOS capacitors formed in the thinned wafer without IG layer were seriously degraded after annealed at 200°C. The DP stress-relief EG layer at the backside of the thinned wafer exhibited good Cu retardation performance. The C-t curves of the MOS trench capacitor with 10-nm thick Ta barrier layer in Cu TSV were severely degraded after the initial annealing at 300°C for 5min. The degraded C-t curve indicates that the generation lifetime of minority carrier is significantly reduced by Cu contamination.