4-bit SFQ multiplier based on booth encoder

Ryosuke Nakamoto; Sakae Sakuraba; Takeshi Onomi; Shigeo Sato; Koji Nakajima

doi:10.1109/TASC.2010.2095814

4-bit SFQ multiplier based on booth encoder

Ryosuke Nakamoto, Sakae Sakuraba, Takeshi Onomi, Shigeo Sato, Koji Nakajima

RIEC - Computing System Platforms Division

Tohoku University

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.

Original language	English
Article number	5680955
Pages (from-to)	852-855
Number of pages	4
Journal	IEEE Transactions on Applied Superconductivity
Volume	21
Issue number	3 PART 1
DOIs	https://doi.org/10.1109/TASC.2010.2095814
Publication status	Published - 2011 Jun

Keywords

FFT
Multiplier
SFQ
Superconductive circuits

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10.1109/TASC.2010.2095814

Cite this

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title = "4-bit SFQ multiplier based on booth encoder",

abstract = "We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.",

keywords = "FFT, Multiplier, SFQ, Superconductive circuits",

author = "Ryosuke Nakamoto and Sakae Sakuraba and Takeshi Onomi and Shigeo Sato and Koji Nakajima",

note = "Funding Information: Manuscript received August 03, 2010; accepted November 19, 2010. Date of publication January 06, 2011; date of current version May 27, 2011. This work was supported in part by MEXT SFQ Project, Scientific Research on Priority Areas entitled “Single-Flux-Quantum Integrated Circuits Based on Localized Electromagnetic Waves,” in 2006–2009.",

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doi = "10.1109/TASC.2010.2095814",

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AU - Sakuraba, Sakae

AU - Onomi, Takeshi

AU - Sato, Shigeo

AU - Nakajima, Koji

N1 - Funding Information: Manuscript received August 03, 2010; accepted November 19, 2010. Date of publication January 06, 2011; date of current version May 27, 2011. This work was supported in part by MEXT SFQ Project, Scientific Research on Priority Areas entitled “Single-Flux-Quantum Integrated Circuits Based on Localized Electromagnetic Waves,” in 2006–2009.

PY - 2011/6

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N2 - We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.

AB - We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.

KW - FFT

KW - Multiplier

KW - SFQ

KW - Superconductive circuits

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4-bit SFQ multiplier based on booth encoder

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Keywords

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