46Gbit/s super-dynamic decision circuit module using InAlAs/InGaAs HEMTs

M. Yoneyama; T. Otsuji; Y. Imai; S. Yamaguchi; T. Enoki; Y. Umeda; K. Hagimoto

doi:10.1049/el:19971007

46Gbit/s super-dynamic decision circuit module using InAlAs/InGaAs HEMTs

M. Yoneyama, T. Otsuji, Y. Imai, S. Yamaguchi, T. Enoki, Y. Umeda, K. Hagimoto

RIEC - Information Communication Platforms Division

Nippon Telegraph & Telephone

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

The authors describe a 46Gbit/s super-dynamic type decision circuit module that uses InAlAs/InGaAs HEMTs. At a data rate of 40Gbit/s, the module shows an input data sensitivity of 104mV_pp and a clock phase margin of 212°.

Original language	English
Pages (from-to)	1472-1474
Number of pages	3
Journal	Electronics Letters
Volume	33
Issue number	17
DOIs	https://doi.org/10.1049/el:19971007
Publication status	Published - 1997 Aug 14

Keywords

Decision circuits
High electron mobility transistors

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10.1049/el:19971007

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title = "46Gbit/s super-dynamic decision circuit module using InAlAs/InGaAs HEMTs",

abstract = "The authors describe a 46Gbit/s super-dynamic type decision circuit module that uses InAlAs/InGaAs HEMTs. At a data rate of 40Gbit/s, the module shows an input data sensitivity of 104mVpp and a clock phase margin of 212°.",

keywords = "Decision circuits, High electron mobility transistors",

author = "M. Yoneyama and T. Otsuji and Y. Imai and S. Yamaguchi and T. Enoki and Y. Umeda and K. Hagimoto",

year = "1997",

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AU - Yoneyama, M.

AU - Otsuji, T.

AU - Imai, Y.

AU - Yamaguchi, S.

AU - Enoki, T.

AU - Umeda, Y.

AU - Hagimoto, K.

PY - 1997/8/14

Y1 - 1997/8/14

N2 - The authors describe a 46Gbit/s super-dynamic type decision circuit module that uses InAlAs/InGaAs HEMTs. At a data rate of 40Gbit/s, the module shows an input data sensitivity of 104mVpp and a clock phase margin of 212°.

AB - The authors describe a 46Gbit/s super-dynamic type decision circuit module that uses InAlAs/InGaAs HEMTs. At a data rate of 40Gbit/s, the module shows an input data sensitivity of 104mVpp and a clock phase margin of 212°.

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KW - High electron mobility transistors

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46Gbit/s super-dynamic decision circuit module using InAlAs/InGaAs HEMTs

Abstract

Keywords

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