4.8 GHz CMOS frequency multiplier using subharmonic pulse-injection locking for spurious suppression

To realize low-power wireless transceivers, it is necessary to improve the performance of frequency synthesizers, which are typically frequency multipliers composed of a phase-locked loop (PLL). However, PLLs generally consume a large amount of power and occupy a large area. To improve the frequency multiplier, we propose a pulse- injection-locked frequency multiplier (PILFM), where a spurious signal is suppressed using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18μm 1P5M CMOS process. The core size is 10.8μm X 10.5 μm. The power consumption of the ILO is 9.6μWat 250 MHz, 255μW at 2.4 GHz and 1.47 mW at 4.8 GHz. The phase noise is -105 dBc/Hz at a 1 MHz offset.