A 0.13-μm, 0.78-μm2 low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

Akira Kotabe; Kenichi Osada; Naoki Kitai; Mio Fujioka; Shiro Kamohara; Masahiro Moniwa; Sadayuki Morita; Yoshikazu Saitoh

A 0.13-μm, 0.78-μm² low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh

Research output: Contribution to conference › Paper › peer-review

3 Citations (Scopus)

Abstract

We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size - fabricated by using 0.13-μm technology - is 0. 78 μm², that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.

Original language	English
Pages	60-63
Number of pages	4
Publication status	Published - 2004 Sept 29
Event	2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States Duration: 2004 Jun 17 → 2004 Jun 19

Other

Other	2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI
Country/Territory	United States
City	Honolulu, HI
Period	04/6/17 → 04/6/19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

A 0.13-μm, 0.78-μm² low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme. / Kotabe, Akira; Osada, Kenichi; Kitai, Naoki et al.

2004. 60-63 Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States.

Research output: Contribution to conference › Paper › peer-review

Kotabe, A, Osada, K, Kitai, N, Fujioka, M, Kamohara, S, Moniwa, M, Morita, S & Saitoh, Y 2004, 'A 0.13-μm, 0.78-μm² low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme', Paper presented at 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI, Honolulu, HI, United States, 04/6/17 - 04/6/19 pp. 60-63.

@conference{85f84b1a3c034d9691bc51118f9c47a0,

title = "A 0.13-μm, 0.78-μm2 low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme",

abstract = "We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size - fabricated by using 0.13-μm technology - is 0. 78 μm2, that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.",

author = "Akira Kotabe and Kenichi Osada and Naoki Kitai and Mio Fujioka and Shiro Kamohara and Masahiro Moniwa and Sadayuki Morita and Yoshikazu Saitoh",

year = "2004",

month = sep,

day = "29",

language = "English",

pages = "60--63",

note = "2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI ; Conference date: 17-06-2004 Through 19-06-2004",

}

TY - CONF

T1 - A 0.13-μm, 0.78-μm2 low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

AU - Kotabe, Akira

AU - Osada, Kenichi

AU - Kitai, Naoki

AU - Fujioka, Mio

AU - Kamohara, Shiro

AU - Moniwa, Masahiro

AU - Morita, Sadayuki

AU - Saitoh, Yoshikazu

PY - 2004/9/29

Y1 - 2004/9/29

N2 - We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size - fabricated by using 0.13-μm technology - is 0. 78 μm2, that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.

AB - We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size - fabricated by using 0.13-μm technology - is 0. 78 μm2, that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.

UR - http://www.scopus.com/inward/record.url?scp=4544300426&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4544300426&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:4544300426

SP - 60

EP - 63

T2 - 2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI

Y2 - 17 June 2004 through 19 June 2004

ER -

A 0.13-μm, 0.78-μm² low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

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