A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

Takahiro Ohnakado; Satoshi Yamakawa; Takaaki Murakami; Akihiko Furukawa; Kazuyasu Nishikawa; Eiji Taniguchi; Hiroomi Ueda; Masayoshi Ono; Jun Tomisawa; Yoshikazu Yoneda; Yasushi Hashizume; Kazuyuki Sugahara; Noriharu Suematsu; Tatsuo Oomori

doi:10.1109/LED.2003.811404

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

Takahiro Ohnakado, Satoshi Yamakawa, Takaaki Murakami, Akihiko Furukawa, Kazuyasu Nishikawa, Eiji Taniguchi, Hiroomi Ueda, Masayoshi Ono, Jun Tomisawa, Yoshikazu Yoneda, Yasushi Hashizume, Kazuyuki Sugahara, Noriharu Suematsu, Tatsuo Oomori

RIEC - Information Communication Platforms Division

Mitsubishi Electric Corporation

Research output: Contribution to journal › Letter › peer-review

5 Citations (Scopus)

Abstract

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 μm CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.

Original language	English
Pages (from-to)	192-194
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	24
Issue number	3
DOIs	https://doi.org/10.1109/LED.2003.811404
Publication status	Published - 2003 Mar

Keywords

CMOS integrated circuits
MOSFETS
Microwave circuits
Microwave devices
Switches

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10.1109/LED.2003.811404

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Ohnakado, T., Yamakawa, S., Murakami, T., Furukawa, A., Nishikawa, K., Taniguchi, E., Ueda, H., Ono, M., Tomisawa, J., Yoneda, Y., Hashizume, Y., Sugahara, K., Suematsu, N., & Oomori, T. (2003). A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process. IEEE Electron Device Letters, 24(3), 192-194. https://doi.org/10.1109/LED.2003.811404

@article{c4a340c7fea04fb186873cc62b1fa282,

title = "A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process",

abstract = "An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 μm CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.",

keywords = "CMOS integrated circuits, MOSFETS, Microwave circuits, Microwave devices, Switches",

author = "Takahiro Ohnakado and Satoshi Yamakawa and Takaaki Murakami and Akihiko Furukawa and Kazuyasu Nishikawa and Eiji Taniguchi and Hiroomi Ueda and Masayoshi Ono and Jun Tomisawa and Yoshikazu Yoneda and Yasushi Hashizume and Kazuyuki Sugahara and Noriharu Suematsu and Tatsuo Oomori",

year = "2003",

month = mar,

doi = "10.1109/LED.2003.811404",

language = "English",

volume = "24",

pages = "192--194",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

Ohnakado, T, Yamakawa, S, Murakami, T, Furukawa, A, Nishikawa, K, Taniguchi, E, Ueda, H, Ono, M, Tomisawa, J, Yoneda, Y, Hashizume, Y, Sugahara, K, Suematsu, N & Oomori, T 2003, 'A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process', IEEE Electron Device Letters, vol. 24, no. 3, pp. 192-194. https://doi.org/10.1109/LED.2003.811404

TY - JOUR

T1 - A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

AU - Ohnakado, Takahiro

AU - Yamakawa, Satoshi

AU - Murakami, Takaaki

AU - Furukawa, Akihiko

AU - Nishikawa, Kazuyasu

AU - Taniguchi, Eiji

AU - Ueda, Hiroomi

AU - Ono, Masayoshi

AU - Tomisawa, Jun

AU - Yoneda, Yoshikazu

AU - Hashizume, Yasushi

AU - Sugahara, Kazuyuki

AU - Suematsu, Noriharu

AU - Oomori, Tatsuo

PY - 2003/3

Y1 - 2003/3

N2 - An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 μm CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.

AB - An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 μm CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.

KW - CMOS integrated circuits

KW - MOSFETS

KW - Microwave circuits

KW - Microwave devices

KW - Switches

UR - http://www.scopus.com/inward/record.url?scp=0038005433&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038005433&partnerID=8YFLogxK

U2 - 10.1109/LED.2003.811404

DO - 10.1109/LED.2003.811404

M3 - Letter

AN - SCOPUS:0038005433

SN - 0741-3106

VL - 24

SP - 192

EP - 194

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 3

ER -

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

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