TY - GEN
T1 - A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories
AU - Ohsawa, T.
AU - Miura, S.
AU - Kinoshita, K.
AU - Honjo, H.
AU - Ikeda, S.
AU - Hanyu, T.
AU - Ohno, H.
AU - Endoh, T.
PY - 2013
Y1 - 2013
N2 - A 1Mb STT-RAM with a 6T2MTJ cell is designed and fabricated using 90nm CMOS/MTJ process that can operate in 1.5nsec/2.1nsec random read/write cycle by adopting a background write scheme. It works around the problem of high error rate of MTJ switching in a short period of time at moderate drive current. The RAM is fast enough to be applicable to embedded memories such as L3 cache.
AB - A 1Mb STT-RAM with a 6T2MTJ cell is designed and fabricated using 90nm CMOS/MTJ process that can operate in 1.5nsec/2.1nsec random read/write cycle by adopting a background write scheme. It works around the problem of high error rate of MTJ switching in a short period of time at moderate drive current. The RAM is fast enough to be applicable to embedded memories such as L3 cache.
UR - http://www.scopus.com/inward/record.url?scp=84883772673&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84883772673&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84883772673
SN - 9784863483484
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C110-C111
BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
T2 - 2013 Symposium on VLSI Circuits, VLSIC 2013
Y2 - 12 June 2013 through 14 June 2013
ER -