A 1Mb STT-RAM with a 6T2MTJ cell is designed and fabricated using 90nm CMOS/MTJ process that can operate in 1.5nsec/2.1nsec random read/write cycle by adopting a background write scheme. It works around the problem of high error rate of MTJ switching in a short period of time at moderate drive current. The RAM is fast enough to be applicable to embedded memories such as L3 cache.
|Title of host publication||2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers|
|Publication status||Published - 2013|
|Event||2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan|
Duration: 2013 Jun 12 → 2013 Jun 14
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||2013 Symposium on VLSI Circuits, VLSIC 2013|
|Period||13/6/12 → 13/6/14|