A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry

Akira Mochizuki; Takahiro Hanyu

doi:10.1109/VLSIC.2005.1469382

A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry

Akira Mochizuki, Takahiro Hanyu

RIEC - Computing System Platforms Division

Tohoku University

Research output: Contribution to conference › Paper › peer-review

13 Citations (Scopus)

Abstract

This paper presents a new 54 × 54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multi-level current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm² die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.

Original language	English
Pages	264-267
Number of pages	4
DOIs	https://doi.org/10.1109/VLSIC.2005.1469382
Publication status	Published - 2005
Event	2005 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2005 Jun 16 → 2005 Jun 18

Conference

Conference	2005 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	05/6/16 → 05/6/18

Keywords

Conditional sum adder and crosstalk noise reduction
Current-mode logic
Signed-digit number

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10.1109/VLSIC.2005.1469382

Cite this

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title = "A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry",

abstract = "This paper presents a new 54 × 54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multi-level current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm2 die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.",

keywords = "Conditional sum adder and crosstalk noise reduction, Current-mode logic, Signed-digit number",

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doi = "10.1109/VLSIC.2005.1469382",

language = "English",

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AU - Mochizuki, Akira

AU - Hanyu, Takahiro

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N2 - This paper presents a new 54 × 54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multi-level current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm2 die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.

AB - This paper presents a new 54 × 54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multi-level current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm2 die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.

KW - Conditional sum adder and crosstalk noise reduction

KW - Current-mode logic

KW - Signed-digit number

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T2 - 2005 Symposium on VLSI Circuits

Y2 - 16 June 2005 through 18 June 2005

ER -

A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry

Abstract

Conference

Keywords

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