A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor

Noriyuki Miura; Kohei Matsuda; Makoto Nagata; Shivam Bhasin; Ville Yli-Mayry; Naofumi Homma; Yves Mathieu; Tarik Graba; Jean Luc Danger

doi:10.23919/VLSIC.2017.8008502

A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor

Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Ville Yli-Mayry, Naofumi Homma, Yves Mathieu, Tarik Graba, Jean Luc Danger

RIEC - Information Communication Platforms Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Citations (Scopus)

Abstract

An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.

Original language	English
Title of host publication	2017 Symposium on VLSI Circuits, VLSI Circuits 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C266-C267
ISBN (Electronic)	9784863486065
DOIs	https://doi.org/10.23919/VLSIC.2017.8008502
Publication status	Published - 2017 Aug 10
Event	31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan Duration: 2017 Jun 5 → 2017 Jun 8

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	31st Symposium on VLSI Circuits, VLSI Circuits 2017
Country/Territory	Japan
City	Kyoto
Period	17/6/5 → 17/6/8

Access to Document

10.23919/VLSIC.2017.8008502

Cite this

Miura, N., Matsuda, K., Nagata, M., Bhasin, S., Yli-Mayry, V., Homma, N., Mathieu, Y., Graba, T., & Danger, J. L. (2017). A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C266-C267). Article 8008502 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008502

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abstract = "An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.",

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Miura, N, Matsuda, K, Nagata, M, Bhasin, S, Yli-Mayry, V, Homma, N, Mathieu, Y, Graba, T & Danger, JL 2017, A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008502, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. C266-C267, 31st Symposium on VLSI Circuits, VLSI Circuits 2017, Kyoto, Japan, 17/6/5. https://doi.org/10.23919/VLSIC.2017.8008502

A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. / Miura, Noriyuki; Matsuda, Kohei; Nagata, Makoto et al.
2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. C266-C267 8008502 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Miura N, Matsuda K, Nagata M, Bhasin S, Yli-Mayry V, Homma N et al. A 2.5ns-latency 0.39pJ/b 289μm²/Gb/s ultra-light-weight PRINCE cryptographic processor. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. C266-C267. 8008502. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSIC.2017.8008502