A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme

Riichiro Takemura; Takayuki Kawahara; Katsuya Miura; Hiroyuki Yamamoto; Jun Hayakawa; Nozomu Matsuzaki; Kazuo Ono; Michihiko Yamanouchi; Kenchi Ito; Hiromasa Takahashi; Shoji Ikeda; Haruhiro Hasegawa; Hideyuki Matsuoka; Hideo Ohno

doi:10.1109/JSSC.2010.2040120

A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme

Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno

Research output: Contribution to journal › Article › peer-review

105 Citations (Scopus)

Abstract

A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.

Original language	English
Article number	5437480
Pages (from-to)	869-879
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	45
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2010.2040120
Publication status	Published - 2010 Apr

Keywords

2T1R memory cell
Localized bi-directional write driver
Low-power RAM
Nonvolatile RAM
Spin-transfer torque
TMR
Universal memory

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2010.2040120

Cite this

Takemura, R., Kawahara, T., Miura, K., Yamamoto, H., Hayakawa, J., Matsuzaki, N., Ono, K., Yamanouchi, M., Ito, K., Takahashi, H., Ikeda, S., Hasegawa, H., Matsuoka, H., & Ohno, H. (2010). A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme. IEEE Journal of Solid-State Circuits, 45(4), 869-879. [5437480]. https://doi.org/10.1109/JSSC.2010.2040120

Takemura, R, Kawahara, T, Miura, K, Yamamoto, H, Hayakawa, J, Matsuzaki, N, Ono, K, Yamanouchi, M, Ito, K, Takahashi, H, Ikeda, S, Hasegawa, H, Matsuoka, H & Ohno, H 2010, 'A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme', IEEE Journal of Solid-State Circuits, vol. 45, no. 4, 5437480, pp. 869-879. https://doi.org/10.1109/JSSC.2010.2040120

@article{04050d2a7823459ab037449936e5fe08,

title = "A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme",

abstract = "A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.",

keywords = "2T1R memory cell, Localized bi-directional write driver, Low-power RAM, Nonvolatile RAM, Spin-transfer torque, TMR, Universal memory",

author = "Riichiro Takemura and Takayuki Kawahara and Katsuya Miura and Hiroyuki Yamamoto and Jun Hayakawa and Nozomu Matsuzaki and Kazuo Ono and Michihiko Yamanouchi and Kenchi Ito and Hiromasa Takahashi and Shoji Ikeda and Haruhiro Hasegawa and Hideyuki Matsuoka and Hideo Ohno",

note = "Funding Information: Manuscript received August 28, 2009; revised November 22, 2009. Current version published March 24, 2010. This paper was approved by Guest Editor Masayuki Mizuno. This work was supported in part by the High-Performance Low-Power Consumption Spin Devices and Storage Systems program under Research and Development for Next-Generation Information Technology of MEXT.",

year = "2010",

month = apr,

doi = "10.1109/JSSC.2010.2040120",

language = "English",

volume = "45",

pages = "869--879",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme

AU - Takemura, Riichiro

AU - Kawahara, Takayuki

AU - Miura, Katsuya

AU - Yamamoto, Hiroyuki

AU - Hayakawa, Jun

AU - Matsuzaki, Nozomu

AU - Ono, Kazuo

AU - Yamanouchi, Michihiko

AU - Ito, Kenchi

AU - Takahashi, Hiromasa

AU - Ikeda, Shoji

AU - Hasegawa, Haruhiro

AU - Matsuoka, Hideyuki

AU - Ohno, Hideo

N1 - Funding Information: Manuscript received August 28, 2009; revised November 22, 2009. Current version published March 24, 2010. This paper was approved by Guest Editor Masayuki Mizuno. This work was supported in part by the High-Performance Low-Power Consumption Spin Devices and Storage Systems program under Research and Development for Next-Generation Information Technology of MEXT.

PY - 2010/4

Y1 - 2010/4

N2 - A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.

AB - A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ns at a supply voltage of 1.8 V. The chip was fabricated with 150-nm CMOS and a 100 × 200-nm tunnel magneto-resistive (TMR) device element. A required thermal stability of 67 of the TMR device was estimated by taking into account the disturbances during read operations and data retention periods of 10 years for nonvolatile operation. The 32-Mb SPRAM chip features three circuit technologies suitable for a large-scale array: 1) a two-transistor, one-resistor (2T1R) type memory cell for achieving a sufficiently large write current despite the small cell size, 2) a compact read/write separated hierarchy bit/source-line structure with a localized bi-directional write driver for efficiently distributing write current, and 3) a '1'/'0' dual-array equalized reference scheme for stable read operation.

KW - 2T1R memory cell

KW - Localized bi-directional write driver

KW - Low-power RAM

KW - Nonvolatile RAM

KW - Spin-transfer torque

KW - TMR

KW - Universal memory

UR - http://www.scopus.com/inward/record.url?scp=77950229376&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77950229376&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2010.2040120

DO - 10.1109/JSSC.2010.2040120

M3 - Article

AN - SCOPUS:77950229376

SN - 0018-9200

VL - 45

SP - 869

EP - 879

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

M1 - 5437480

ER -

A 32-Mb SPRAM with 2T1R memory cell, localized bi-directional write driver and '1'/'0' dual-array equalized reference scheme

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this