A 35-GHz 20- μm2 self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs

Katsuyoslii Washio; K. Hiromi Shimamoto; Toliru Nakainura

doi:10.1109/VLSIT.1992.200692

A 35-GHz 20- μm² self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs

Katsuyoslii Washio, K. Hiromi Shimamoto, Toliru Nakainura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

An ultra-high-speed high-density self-aligned pup technology for complementary bipolar ULSIs has been developed which is fully compatible wilh the npn process. Low sheet-resistance p+ buried layer and extrinsic n+ polysilicon layer with U-grooved isolation enable transistor size to be sealed down to about 20 μm2. A shallow emitter junction depth of 45 nm and narrow hase width of 30 nm improve maximum cutoff frequency to 35 GHz The power dissipation of pnp pulldown complementary emitter-follower ECL circuit for the loaded ease is calculated lo be reduced to 1/5 compared with the conventional ECL circuit.

Original language	English
Title of host publication	1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	64-65
Number of pages	2
ISBN (Electronic)	0780306988
DOIs	https://doi.org/10.1109/VLSIT.1992.200692
Publication status	Published - 1992
Externally published	Yes
Event	1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992 - Seattle, United States Duration: 1992 Jun 2 → 1992 Jun 4

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	1992-June
ISSN (Print)	0743-1562

Conference

Conference	1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992
Country/Territory	United States
City	Seattle
Period	92/6/2 → 92/6/4

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.1992.200692

Cite this

Washio, K., Shimamoto, K. H., & Nakainura, T. (1992). A 35-GHz 20- μm² self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs. In 1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992 (pp. 64-65). [200692] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 1992-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.1992.200692

A 35-GHz 20- μm² self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs. / Washio, Katsuyoslii; Shimamoto, K. Hiromi; Nakainura, Toliru.
1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 64-65 200692 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 1992-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Washio, K, Shimamoto, KH & Nakainura, T 1992, A 35-GHz 20- μm² self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs. in 1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992., 200692, Digest of Technical Papers - Symposium on VLSI Technology, vol. 1992-June, Institute of Electrical and Electronics Engineers Inc., pp. 64-65, 1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992, Seattle, United States, 92/6/2. https://doi.org/10.1109/VLSIT.1992.200692

Washio K, Shimamoto KH, Nakainura T. A 35-GHz 20- μm² self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs. In 1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 64-65. 200692. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.1992.200692

Washio, Katsuyoslii ; Shimamoto, K. Hiromi ; Nakainura, Toliru. / A 35-GHz 20- μm² self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs. 1992 Symposium on VLSI Technology - Digest of Technical Papers, VLSI Technology 1992. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 64-65 (Digest of Technical Papers - Symposium on VLSI Technology).

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