A 500-MHz MRAM macro for high-performance SoCs

Noboru Sakimura; Ryusuke Nebashi; Hiroaki Honjo; Shinsaku Saito; Yuko Kato; Tadahiko Sugibayashi

doi:10.1109/ASSCC.2008.4708778

A 500-MHz MRAM macro for high-performance SoCs

Noboru Sakimura, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Tadahiko Sugibayashi

Center for Innovative Integrated Electronic Systems (CIES)

NEC Corporation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Citations (Scopus)

Abstract

A 500-MHz MRAM macro is developed using a 0.15-μm CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-μm ² 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TlMTJ-cell-based MRAM macro in SoCs.

Original language	English
Title of host publication	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages	261-264
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2008.4708778
Publication status	Published - 2008
Event	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan Duration: 2008 Nov 3 → 2008 Nov 5

Publication series

Name	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Conference

Conference	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Country/Territory	Japan
City	Fukuoka
Period	08/11/3 → 08/11/5

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10.1109/ASSCC.2008.4708778

Cite this

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title = "A 500-MHz MRAM macro for high-performance SoCs",

abstract = "A 500-MHz MRAM macro is developed using a 0.15-μm CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-μm 2 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TlMTJ-cell-based MRAM macro in SoCs.",

author = "Noboru Sakimura and Ryusuke Nebashi and Hiroaki Honjo and Shinsaku Saito and Yuko Kato and Tadahiko Sugibayashi",

year = "2008",

doi = "10.1109/ASSCC.2008.4708778",

language = "English",

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series = "Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008",

pages = "261--264",

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note = "2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 ; Conference date: 03-11-2008 Through 05-11-2008",

}

Sakimura, N, Nebashi, R, Honjo, H, Saito, S, Kato, Y & Sugibayashi, T 2008, A 500-MHz MRAM macro for high-performance SoCs. in Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008., 4708778, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp. 261-264, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, Fukuoka, Japan, 08/11/3. https://doi.org/10.1109/ASSCC.2008.4708778

A 500-MHz MRAM macro for high-performance SoCs. / Sakimura, Noboru; Nebashi, Ryusuke; Honjo, Hiroaki et al.
Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. 2008. p. 261-264 4708778 (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A 500-MHz MRAM macro for high-performance SoCs

AU - Sakimura, Noboru

AU - Nebashi, Ryusuke

AU - Honjo, Hiroaki

AU - Saito, Shinsaku

AU - Kato, Yuko

AU - Sugibayashi, Tadahiko

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AB - A 500-MHz MRAM macro is developed using a 0.15-μm CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-μm 2 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TlMTJ-cell-based MRAM macro in SoCs.

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A 500-MHz MRAM macro for high-performance SoCs

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