A 55-ns 16-Mb DRAM with Built-in Self-Test Function Using Microprogram ROM

Toshio Takeshima; Masahide Takada; Hiroki Koike; Hiroshi Watanabe; Shigeru Koshimaru; Kenjiro Mitake; Wataru Kikuchi; Takaho Tanigawa; Tatsunori Murotani; Kenji Noda; Kazuhiro Tasaka; Koji Yamanaka; Kuniaki Koyama

doi:10.1109/4.58282

A 55-ns 16-Mb DRAM with Built-in Self-Test Function Using Microprogram ROM

Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama

Center for Innovative Integrated Electronic Systems (CIES)

NEC Corporation

Research output: Contribution to journal › Article › peer-review

11 Citations (Scopus)

Abstract

A single 5-V power supply 16-Mb dynamic random access memory (DRAM) has been developed, using a high-speed latched sensing scheme and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level A1 wiring 0.55-µm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm2 chip area was attained by implementing 4.05-µm2 storage ceils. The installed ROM was composed of 18 words ×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupied 1 mm2 and the area overhead was about 1%, it proves to be promising for large-scale DRAM’s.

Original language	English
Pages (from-to)	903-911
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	25
Issue number	4
DOIs	https://doi.org/10.1109/4.58282
Publication status	Published - 1990 Aug

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title = "A 55-ns 16-Mb DRAM with Built-in Self-Test Function Using Microprogram ROM",

abstract = "A single 5-V power supply 16-Mb dynamic random access memory (DRAM) has been developed, using a high-speed latched sensing scheme and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level A1 wiring 0.55-µm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm2 chip area was attained by implementing 4.05-µm2 storage ceils. The installed ROM was composed of 18 words ×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupied 1 mm2 and the area overhead was about 1%, it proves to be promising for large-scale DRAM{\textquoteright}s.",

author = "Toshio Takeshima and Masahide Takada and Hiroki Koike and Hiroshi Watanabe and Shigeru Koshimaru and Kenjiro Mitake and Wataru Kikuchi and Takaho Tanigawa and Tatsunori Murotani and Kenji Noda and Kazuhiro Tasaka and Koji Yamanaka and Kuniaki Koyama",

year = "1990",

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AU - Takeshima, Toshio

AU - Takada, Masahide

AU - Koike, Hiroki

AU - Watanabe, Hiroshi

AU - Koshimaru, Shigeru

AU - Mitake, Kenjiro

AU - Kikuchi, Wataru

AU - Tanigawa, Takaho

AU - Murotani, Tatsunori

AU - Noda, Kenji

AU - Tasaka, Kazuhiro

AU - Yamanaka, Koji

AU - Koyama, Kuniaki

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A 55-ns 16-Mb DRAM with Built-in Self-Test Function Using Microprogram ROM

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