A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm2 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications

Satoshi Nakai; Manabu Kojima; Nobuhiro Misawa; Motoshu Miyajima; Satoru Asai; Satoshi Inagaki; Yoshihisa Iba; Takayuki Ohba; Masataka Kase; Hideki Kitada; Shigeo Satoh; Noriyoshi Shimizu; Iwao Sugiura; Fumitoshi Sugimoto; Yuji Setta; Tetsu Tanaka; Naoyoshi Tamura; Masafumi Nakaishi; Yoshihiro Nakata; Junya Nakahira; Nobuyuki Nishikawa; Akihiro Hasegawa; Shunichi Fukuyama; Kazushi Fujita; Kimihiko Hosaka; Naoto Horiguchi; Hideya Matsuyama; Takayoshi Minami; Masaharu Minamizawa; Hiroshi Morioka; Ei Yano; Akihisa Yamaguchi; Kiyoshi Watanabe; Tomoji Nakamura; Toshihiro Sugii

A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm² 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications

Satoshi Nakai, Manabu Kojima, Nobuhiro Misawa, Motoshu Miyajima, Satoru Asai, Satoshi Inagaki, Yoshihisa Iba, Takayuki Ohba, Masataka Kase, Hideki Kitada, Shigeo Satoh, Noriyoshi Shimizu, Iwao Sugiura, Fumitoshi Sugimoto, Yuji Setta, Tetsu Tanaka, Naoyoshi Tamura, Masafumi Nakaishi, Yoshihiro Nakata, Junya NakahiraNobuyuki Nishikawa, Akihiro Hasegawa, Shunichi Fukuyama, Kazushi Fujita, Kimihiko Hosaka, Naoto Horiguchi, Hideya Matsuyama, Takayoshi Minami, Masaharu Minamizawa, Hiroshi Morioka, Ei Yano, Akihisa Yamaguchi, Kiyoshi Watanabe, Tomoji Nakamura, Toshihiro Sugii

Research output: Contribution to journal › Conference article › peer-review

16 Citations (Scopus)

Abstract

This paper presents a 65 nm CMOS technology for mobile multimedia applications. To reduce capacitance of inter-connects is essential to high-speed data transmission and small power consumption for mobile core chips. We have chosen hybrid ULK structure which consists of NCS (nano-clustering silica (1); k=2.25) at wire level and SiOC (k=2.9) at via level. Although NCS is one of porous materials, NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bondings. Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistor meet the electrical target from circuit requirements. Moreover, an embedded 6T-SRAM with a 0.55 μm² small cell size has been achieved.

Original language	English
Pages (from-to)	285-288
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 2003 Dec 1
Externally published	Yes
Event	IEEE International Electron Devices Meeting - Washington, DC, United States Duration: 2003 Dec 8 → 2003 Dec 10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

Nakai, S., Kojima, M., Misawa, N., Miyajima, M., Asai, S., Inagaki, S., Iba, Y., Ohba, T., Kase, M., Kitada, H., Satoh, S., Shimizu, N., Sugiura, I., Sugimoto, F., Setta, Y., Tanaka, T., Tamura, N., Nakaishi, M., Nakata, Y., ... Sugii, T. (2003). A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm² 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications. Technical Digest - International Electron Devices Meeting, 285-288.

A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm² 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications. / Nakai, Satoshi; Kojima, Manabu; Misawa, Nobuhiro et al.
In: Technical Digest - International Electron Devices Meeting, 01.12.2003, p. 285-288.

Research output: Contribution to journal › Conference article › peer-review

Nakai, S, Kojima, M, Misawa, N, Miyajima, M, Asai, S, Inagaki, S, Iba, Y, Ohba, T, Kase, M, Kitada, H, Satoh, S, Shimizu, N, Sugiura, I, Sugimoto, F, Setta, Y, Tanaka, T, Tamura, N, Nakaishi, M, Nakata, Y, Nakahira, J, Nishikawa, N, Hasegawa, A, Fukuyama, S, Fujita, K, Hosaka, K, Horiguchi, N, Matsuyama, H, Minami, T, Minamizawa, M, Morioka, H, Yano, E, Yamaguchi, A, Watanabe, K, Nakamura, T & Sugii, T 2003, 'A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm² 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications', Technical Digest - International Electron Devices Meeting, pp. 285-288.

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title = "A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm2 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications",

abstract = "This paper presents a 65 nm CMOS technology for mobile multimedia applications. To reduce capacitance of inter-connects is essential to high-speed data transmission and small power consumption for mobile core chips. We have chosen hybrid ULK structure which consists of NCS (nano-clustering silica (1); k=2.25) at wire level and SiOC (k=2.9) at via level. Although NCS is one of porous materials, NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bondings. Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistor meet the electrical target from circuit requirements. Moreover, an embedded 6T-SRAM with a 0.55 μm2 small cell size has been achieved.",

author = "Satoshi Nakai and Manabu Kojima and Nobuhiro Misawa and Motoshu Miyajima and Satoru Asai and Satoshi Inagaki and Yoshihisa Iba and Takayuki Ohba and Masataka Kase and Hideki Kitada and Shigeo Satoh and Noriyoshi Shimizu and Iwao Sugiura and Fumitoshi Sugimoto and Yuji Setta and Tetsu Tanaka and Naoyoshi Tamura and Masafumi Nakaishi and Yoshihiro Nakata and Junya Nakahira and Nobuyuki Nishikawa and Akihiro Hasegawa and Shunichi Fukuyama and Kazushi Fujita and Kimihiko Hosaka and Naoto Horiguchi and Hideya Matsuyama and Takayoshi Minami and Masaharu Minamizawa and Hiroshi Morioka and Ei Yano and Akihisa Yamaguchi and Kiyoshi Watanabe and Tomoji Nakamura and Toshihiro Sugii",

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AU - Nakai, Satoshi

AU - Kojima, Manabu

AU - Misawa, Nobuhiro

AU - Miyajima, Motoshu

AU - Asai, Satoru

AU - Inagaki, Satoshi

AU - Iba, Yoshihisa

AU - Ohba, Takayuki

AU - Kase, Masataka

AU - Kitada, Hideki

AU - Satoh, Shigeo

AU - Shimizu, Noriyoshi

AU - Sugiura, Iwao

AU - Sugimoto, Fumitoshi

AU - Setta, Yuji

AU - Tanaka, Tetsu

AU - Tamura, Naoyoshi

AU - Nakaishi, Masafumi

AU - Nakata, Yoshihiro

AU - Nakahira, Junya

AU - Nishikawa, Nobuyuki

AU - Hasegawa, Akihiro

AU - Fukuyama, Shunichi

AU - Fujita, Kazushi

AU - Hosaka, Kimihiko

AU - Horiguchi, Naoto

AU - Matsuyama, Hideya

AU - Minami, Takayoshi

AU - Minamizawa, Masaharu

AU - Morioka, Hiroshi

AU - Yano, Ei

AU - Yamaguchi, Akihisa

AU - Watanabe, Kiyoshi

AU - Nakamura, Tomoji

AU - Sugii, Toshihiro

PY - 2003/12/1

Y1 - 2003/12/1

N2 - This paper presents a 65 nm CMOS technology for mobile multimedia applications. To reduce capacitance of inter-connects is essential to high-speed data transmission and small power consumption for mobile core chips. We have chosen hybrid ULK structure which consists of NCS (nano-clustering silica (1); k=2.25) at wire level and SiOC (k=2.9) at via level. Although NCS is one of porous materials, NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bondings. Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistor meet the electrical target from circuit requirements. Moreover, an embedded 6T-SRAM with a 0.55 μm2 small cell size has been achieved.

AB - This paper presents a 65 nm CMOS technology for mobile multimedia applications. To reduce capacitance of inter-connects is essential to high-speed data transmission and small power consumption for mobile core chips. We have chosen hybrid ULK structure which consists of NCS (nano-clustering silica (1); k=2.25) at wire level and SiOC (k=2.9) at via level. Although NCS is one of porous materials, NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bondings. Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistor meet the electrical target from circuit requirements. Moreover, an embedded 6T-SRAM with a 0.55 μm2 small cell size has been achieved.

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ER -

A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm² 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications

Abstract

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