@inproceedings{2c1ba3feb4474f338b7bdfd0e561036b,
title = "A cache partitioning mechanism to protect shared data for CMPs",
abstract = "The last-level cache (LLC) of a modern chip-multiprocessor (CMP) keeps two kinds of data: shared data accessed by multiple cores and private data accessed by only one core. Although the former are likely to have a larger performance impact than the latter, the LLC manages both of those data in the same fashion. To realize a highly efficient execution on a CMP, this paper proposes a cache partitioning mechanism to protect shared data from excessive eviction. The evaluation results show that the proposed mechanism improves the performance by up to 76% and by 8% on average at a cost of less than 2% of the LLC hardware.",
keywords = "cache memory, cache partitioning, chip-multiprocessor, shared data",
author = "Masayuki Sato and Shin Nishimura and Ryusuke Egawa and Hiroyuki Takizawa and Hiroaki Kobayashi",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 ; Conference date: 20-04-2016 Through 22-04-2016",
year = "2016",
month = jul,
day = "5",
doi = "10.1109/CoolChips.2016.7503674",
language = "English",
series = "19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings",
address = "United States",
}