A compact and low power logic design for multi-pillar vertical MOSFETs

Koji Sakui; Tetsuo Endoh

doi:10.1109/ISCAS.2010.5537837

A compact and low power logic design for multi-pillar vertical MOSFETs

Koji Sakui, Tetsuo Endoh

ENG - Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

The compact and low power logic circuit design for multi-pillar vertical MOSFETs has been proposed. The proposed design with the multi-pillar vertical MOSFETs is very practical for considering the load capacitance and resistance by changing the number of the silicon pillars flexibly for the desired channel width of series connected MOSFETs and their layout pattern.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	309-312
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537837
Publication status	Published - 2010 Aug 31
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 2010 May 30 → 2010 Jun 2

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	10/5/30 → 10/6/2

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2010.5537837

Cite this

Sakui, K., & Endoh, T. (2010). A compact and low power logic design for multi-pillar vertical MOSFETs. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 309-312). [5537837] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537837

A compact and low power logic design for multi-pillar vertical MOSFETs. / Sakui, Koji; Endoh, Tetsuo.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 309-312 5537837 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sakui, K & Endoh, T 2010, A compact and low power logic design for multi-pillar vertical MOSFETs. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537837, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 309-312, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537837

Sakui K, Endoh T. A compact and low power logic design for multi-pillar vertical MOSFETs. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 309-312. 5537837. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5537837

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A compact and low power logic design for multi-pillar vertical MOSFETs

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