A compact, high-speed, and low-power design for multi-pillar vertical MOSFET's, suppressing characteristic influences by process fluctuation

Pillar-type MOSFET's were studied for over two decades [1][2], however, recent studies found a more practical, affordable way to manufacture them and extract their performance merits by isolating the pillar body from the substrate with the diffusion region [3][4]. a number of papers have come up for their application to the three dimensional Flash memory cells [5]-[7]. However, due to the device structure of the vertical mosfet, the bottom of its silicon pillar has a certain resistance, which causes the asymmetric source/drain characteristics. Furthermore, the practical circuit design with the vertical MOSFET's has not been investigated in details. Unlike the circuit design with the planar MOSFET's, the channel length of L is defined by the gate material deposition depth in process, and the channel width of W is defined by the number of the silicon pillars with a certain fixed diameter. This paper is devoted to investigating the transistor characteristic influences by the silicon pillar diameter thinning due to the process fluctuation, and proposing the compact, high-speed, and low-power circuit design with multi-pillar vertical MOSFET's [8] in order to suppress the pillar thinning influences.