A compact space and efficient drain current design for multipillar vertical MOSFETs

Koji Sakui; Tetsuo Endoh

doi:10.1109/TED.2010.2050546

A compact space and efficient drain current design for multipillar vertical MOSFETs

Koji Sakui, Tetsuo Endoh

ENG - Electrical Engineering

Tohoku University

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

In the vertical MOSFET, due to its device structure, the bottom of its silicon pillar has a certain resistance because there is a diffused silicon wiring area in the bottom. Thereby, this resistance becomes large in the case of the multipillar transistors and also shows asymmetric characteristics between the top and bottom nodes of the pillar. This paper is devoted to examining this resistance for the multipillar vertical MOSFETs and proposing a compact design, which can suppress the resistance influences, attain a large drain current, and achieve a higher circuit performance.

Original language	English
Article number	5491144
Pages (from-to)	1768-1773
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	57
Issue number	8
DOIs	https://doi.org/10.1109/TED.2010.2050546
Publication status	Published - 2010 Aug

Keywords

Bottom node resistance
multipillar MOSFETS
vertical MOSFET

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10.1109/TED.2010.2050546

Cite this

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title = "A compact space and efficient drain current design for multipillar vertical MOSFETs",

abstract = "In the vertical MOSFET, due to its device structure, the bottom of its silicon pillar has a certain resistance because there is a diffused silicon wiring area in the bottom. Thereby, this resistance becomes large in the case of the multipillar transistors and also shows asymmetric characteristics between the top and bottom nodes of the pillar. This paper is devoted to examining this resistance for the multipillar vertical MOSFETs and proposing a compact design, which can suppress the resistance influences, attain a large drain current, and achieve a higher circuit performance.",

keywords = "Bottom node resistance, multipillar MOSFETS, vertical MOSFET",

author = "Koji Sakui and Tetsuo Endoh",

note = "Funding Information: Manuscript received December 18, 2009; revised April 26, 2010; accepted April 28, 2010. Date of publication June 21, 2010; date of current version July 23, 2010. This work was supported in part by a grant from “Research of Innovative Material and Process for Creation of Next-Generation Electronics Devices,” Core Research for Evolutional Science and Technology (CREST), Japan Science and Technology Agency (JST). The review of this paper was arranged by Editor G.-T. Jeong.",

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AU - Endoh, Tetsuo

N1 - Funding Information: Manuscript received December 18, 2009; revised April 26, 2010; accepted April 28, 2010. Date of publication June 21, 2010; date of current version July 23, 2010. This work was supported in part by a grant from “Research of Innovative Material and Process for Creation of Next-Generation Electronics Devices,” Core Research for Evolutional Science and Technology (CREST), Japan Science and Technology Agency (JST). The review of this paper was arranged by Editor G.-T. Jeong.

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N2 - In the vertical MOSFET, due to its device structure, the bottom of its silicon pillar has a certain resistance because there is a diffused silicon wiring area in the bottom. Thereby, this resistance becomes large in the case of the multipillar transistors and also shows asymmetric characteristics between the top and bottom nodes of the pillar. This paper is devoted to examining this resistance for the multipillar vertical MOSFETs and proposing a compact design, which can suppress the resistance influences, attain a large drain current, and achieve a higher circuit performance.

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A compact space and efficient drain current design for multipillar vertical MOSFETs

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Keywords

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