TY - JOUR
T1 - A fail-safe logic operator using an insulated planar transformer
AU - Asada, Norihiro
AU - Matsuki, Hidetoshi
AU - Esashi, Masayoshi
PY - 1994
Y1 - 1994
N2 - A fail-safe logic circuit must switch the output signal to the logical value “0” when the operation circuit fails. Transformer has such favorable characteristics for fail-safe logic circuits that only the magnetic flux change is transmitted and that a superposition of magnetic flux is realized. So we applied those characteristics to a fail-safe logic operator. A new fail-safe logic operator using an insulated planar transformer was developed for a fail-safe majority operation and a fail-safe interlocking. In this paper, the principle, structure, fabrication and fundamental characteristics of the new fail-safe logic operator are described.
AB - A fail-safe logic circuit must switch the output signal to the logical value “0” when the operation circuit fails. Transformer has such favorable characteristics for fail-safe logic circuits that only the magnetic flux change is transmitted and that a superposition of magnetic flux is realized. So we applied those characteristics to a fail-safe logic operator. A new fail-safe logic operator using an insulated planar transformer was developed for a fail-safe majority operation and a fail-safe interlocking. In this paper, the principle, structure, fabrication and fundamental characteristics of the new fail-safe logic operator are described.
UR - http://www.scopus.com/inward/record.url?scp=85007768035&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85007768035&partnerID=8YFLogxK
U2 - 10.1541/ieejias.114.255
DO - 10.1541/ieejias.114.255
M3 - Article
AN - SCOPUS:85007768035
SN - 0913-6339
VL - 114
SP - 255
EP - 259
JO - IEEJ Transactions on Industry Applications
JF - IEEJ Transactions on Industry Applications
IS - 3
ER -