TY - GEN
T1 - A floating-gate-MOS-based multiple-valued associative memory
AU - Hanyu, Takahiro
AU - Higuchi, Tatsuo
PY - 1991/5
Y1 - 1991/5
N2 - A digit-serial, multiple valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.
AB - A digit-serial, multiple valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.
UR - http://www.scopus.com/inward/record.url?scp=0026155388&partnerID=8YFLogxK
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M3 - Conference contribution
AN - SCOPUS:0026155388
SN - 0818621451
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 24
EP - 31
BT - Proceedings of The International Symposium on Multiple-Valued Logic
PB - Publ by IEEE
T2 - Proceedings of the 21st International Symposium on Multiple-Valued Logic
Y2 - 26 May 1991 through 29 May 1991
ER -