TY - GEN
T1 - A low-power field-programmable VLSI based on a fine-grained power-gating scheme
AU - Hariyama, Masanori
AU - Ishihara, Shota
AU - Kameyama, Michitaka
PY - 2008
Y1 - 2008
N2 - This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To reduce the static power due to leakage current that is now comparable to the dynamic one, we propose a fine-grained power-gating scheme at each Lookup table (LUT). The proposed field-programmable VLSI is fabricated in a 90nm CMOS technology. Its power consumption is reduced to 42% compared to synchronous architecture.
AB - This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To reduce the static power due to leakage current that is now comparable to the dynamic one, we propose a fine-grained power-gating scheme at each Lookup table (LUT). The proposed field-programmable VLSI is fabricated in a 90nm CMOS technology. Its power consumption is reduced to 42% compared to synchronous architecture.
UR - http://www.scopus.com/inward/record.url?scp=54249084600&partnerID=8YFLogxK
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U2 - 10.1109/MWSCAS.2008.4616896
DO - 10.1109/MWSCAS.2008.4616896
M3 - Conference contribution
AN - SCOPUS:54249084600
SN - 9781424421671
T3 - Midwest Symposium on Circuits and Systems
SP - 702
EP - 705
BT - 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
T2 - 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Y2 - 10 August 2008 through 13 August 2008
ER -