A low-power FPGA based on autonomous fine-grain power gating

Shota Ishihara, Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

40 Citations (Scopus)


This paper presents a field-programmable gate array (FPGA) based on lookup table level fine-grain power gating with small overheads. The power gating technique implemented in the proposed architecture can directly detect the activity of each look-up-table easily by exploiting features of asynchronous architectures. Moreover, detecting the data arrival in advance prevents the delay increase for waking-up and the power consumption of unnecessary power switching. Since the power gating technique has small overheads, the granularity size of a power-gated domain is as fine as a single two-input and one-output lookup table. The proposed FPGA is fabricated using the ASPLA 90-nm CMOS process with dual threshold voltages. We use an image processing application called template matching for evaluation. Since the proposed FPGA is suitable for processing where the workload changes dynamically, an adaptive algorithm where a small computational kernel is employed. Compared to a synchronous FPGA and an asynchronous FPGA without power gating, the power consumption is reduced respectively by 38% and 15% at 85 °C.

Original languageEnglish
Article number5483137
Pages (from-to)1394-1406
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number8
Publication statusPublished - 2011 Aug


  • Asynchronous architecture
  • asynchronous field-programmable gate array (FPGA)
  • level-encoded dual-rail (LEDR) encoding
  • reconfigurable VLSI
  • self-timed architecture


Dive into the research topics of 'A low-power FPGA based on autonomous fine-grain power gating'. Together they form a unique fingerprint.

Cite this