A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure

Daisuke Suzuki; Takahiro Hanyu

doi:10.1109/FPL.2016.7577345

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure

Daisuke Suzuki, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A nonvolatile field-programmable gate array (NVFPGA), where both magnetic tunnel junction (MTJ) devices and greedy power-saving techniques are utilized, is proposed. Because the circuit components are shared among several MTJ devices by the use of logic-in-memory (LIM) structure, the number of leakage current paths is reduced, which results in leakage power reduction during power-on. Moreover, the use of the self-termination scheme, which automatically turns off the write current immediately after the desired data is written, makes it possible to minimize power consumption during the backup operation. In fact, the proposed NVFPGA exhibits a 90 % power reduction in comparison with that of a conventional SRAM-based FPGA under typical benchmark-circuit implementations.

Original language	English
Title of host publication	FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9782839918442
DOIs	https://doi.org/10.1109/FPL.2016.7577345
Publication status	Published - 2016 Sept 26
Event	26th International Conference on Field-Programmable Logic and Applications, FPL 2016 - Lausanne, Switzerland Duration: 2016 Aug 29 → 2016 Sept 2

Publication series

Name	FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications

Other

Other	26th International Conference on Field-Programmable Logic and Applications, FPL 2016
Country/Territory	Switzerland
City	Lausanne
Period	16/8/29 → 16/9/2

ASJC Scopus subject areas

Computer Networks and Communications
Computer Science Applications
Control and Optimization

Access to Document

10.1109/FPL.2016.7577345

Cite this

Suzuki, D., & Hanyu, T. (2016). A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. In FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications [7577345] (FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2016.7577345

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. / Suzuki, Daisuke; Hanyu, Takahiro.
FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc., 2016. 7577345 (FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Suzuki, D & Hanyu, T 2016, A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. in FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications., 7577345, FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications, Institute of Electrical and Electronics Engineers Inc., 26th International Conference on Field-Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, 16/8/29. https://doi.org/10.1109/FPL.2016.7577345

Suzuki D, Hanyu T. A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. In FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc. 2016. 7577345. (FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications). doi: 10.1109/FPL.2016.7577345

@inproceedings{b773598e5053436a9a0cd47e54d17760,

title = "A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure",

abstract = "A nonvolatile field-programmable gate array (NVFPGA), where both magnetic tunnel junction (MTJ) devices and greedy power-saving techniques are utilized, is proposed. Because the circuit components are shared among several MTJ devices by the use of logic-in-memory (LIM) structure, the number of leakage current paths is reduced, which results in leakage power reduction during power-on. Moreover, the use of the self-termination scheme, which automatically turns off the write current immediately after the desired data is written, makes it possible to minimize power consumption during the backup operation. In fact, the proposed NVFPGA exhibits a 90 % power reduction in comparison with that of a conventional SRAM-based FPGA under typical benchmark-circuit implementations.",

author = "Daisuke Suzuki and Takahiro Hanyu",

note = "Publisher Copyright: {\textcopyright} 2016 EPFL.; 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 ; Conference date: 29-08-2016 Through 02-09-2016",

year = "2016",

month = sep,

day = "26",

doi = "10.1109/FPL.2016.7577345",

language = "English",

series = "FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications",

}

TY - GEN

T1 - A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure

AU - Suzuki, Daisuke

AU - Hanyu, Takahiro

PY - 2016/9/26

Y1 - 2016/9/26

N2 - A nonvolatile field-programmable gate array (NVFPGA), where both magnetic tunnel junction (MTJ) devices and greedy power-saving techniques are utilized, is proposed. Because the circuit components are shared among several MTJ devices by the use of logic-in-memory (LIM) structure, the number of leakage current paths is reduced, which results in leakage power reduction during power-on. Moreover, the use of the self-termination scheme, which automatically turns off the write current immediately after the desired data is written, makes it possible to minimize power consumption during the backup operation. In fact, the proposed NVFPGA exhibits a 90 % power reduction in comparison with that of a conventional SRAM-based FPGA under typical benchmark-circuit implementations.

AB - A nonvolatile field-programmable gate array (NVFPGA), where both magnetic tunnel junction (MTJ) devices and greedy power-saving techniques are utilized, is proposed. Because the circuit components are shared among several MTJ devices by the use of logic-in-memory (LIM) structure, the number of leakage current paths is reduced, which results in leakage power reduction during power-on. Moreover, the use of the self-termination scheme, which automatically turns off the write current immediately after the desired data is written, makes it possible to minimize power consumption during the backup operation. In fact, the proposed NVFPGA exhibits a 90 % power reduction in comparison with that of a conventional SRAM-based FPGA under typical benchmark-circuit implementations.

UR - http://www.scopus.com/inward/record.url?scp=84994896268&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84994896268&partnerID=8YFLogxK

U2 - 10.1109/FPL.2016.7577345

DO - 10.1109/FPL.2016.7577345

M3 - Conference contribution

AN - SCOPUS:84994896268

T3 - FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications

BT - FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 26th International Conference on Field-Programmable Logic and Applications, FPL 2016

Y2 - 29 August 2016 through 2 September 2016

ER -

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure

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