A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers

Jubee Tada; Ryusuke Egawa; Kazushige Kawai; Hiroaki Kobayashi; Gensuke Goto

doi:10.1109/3DIC.2012.6263031

A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers

Jubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi, Gensuke Goto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Three-dimensional (3-D) integration technologies have been expected to overcome the limitations of conventional microprocessors, which integrated by two-dimensional (2-D) implementation technologies. This paper focuses on a circuit partitioning strategy for 3-D integrated circuit designs, because it plays important roles to exploit the potential of 3-D integrated circuits. A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers is proposed and evaluated in this paper. The proposed strategy equalizes the area of each layer and avoids the critical path to across different layers as much as possible A double-precision 3-D integrated floating-point multiplier which designed by the proposed circuit partitioning strategy achieves 42% delay reduction compared to the 2-D implementation.

Original language	English
Title of host publication	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs	https://doi.org/10.1109/3DIC.2012.6263031
Publication status	Published - 2011
Event	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan Duration: 2012 Jan 31 → 2012 Feb 2

Publication series

Name	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Country/Territory	Japan
City	Osaka
Period	12/1/31 → 12/2/2

Keywords

3-D integration
TSV
floating-point arithmetic units

ASJC Scopus subject areas

Control and Systems Engineering

Access to Document

10.1109/3DIC.2012.6263031

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A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers. / Tada, Jubee; Egawa, Ryusuke; Kawai, Kazushige et al.
2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. 2011. 6263031 (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tada, J, Egawa, R, Kawai, K, Kobayashi, H & Goto, G 2011, A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers. in 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011., 6263031, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, Osaka, Japan, 12/1/31. https://doi.org/10.1109/3DIC.2012.6263031

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AB - Three-dimensional (3-D) integration technologies have been expected to overcome the limitations of conventional microprocessors, which integrated by two-dimensional (2-D) implementation technologies. This paper focuses on a circuit partitioning strategy for 3-D integrated circuit designs, because it plays important roles to exploit the potential of 3-D integrated circuits. A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers is proposed and evaluated in this paper. The proposed strategy equalizes the area of each layer and avoids the critical path to across different layers as much as possible A double-precision 3-D integrated floating-point multiplier which designed by the proposed circuit partitioning strategy achieves 42% delay reduction compared to the 2-D implementation.

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A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers

Abstract

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Keywords

ASJC Scopus subject areas

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