TY - GEN
T1 - A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions
AU - Ishigaki, T.
AU - Kawahara, T.
AU - Takemura, R.
AU - Ono, K.
AU - Ito, K.
AU - Matsuoka, H.
AU - Ohno, H.
PY - 2010
Y1 - 2010
N2 - We first report a multi-level-cell (MLC) spin-transfer torque memory (SPRAM) with series-connected magnetotunnel junctions (MTJs). The series MTJs (with different areas) show multi-level resistances by a combination of their magnetization directions. A four-level operation by spin-transfer-torque writing was experimentally demonstrated. A scheme for the write/read operation of the MLC SPRAM was also presented. Keywords: MRAM, SPRAM, spin, multi-bit, and MLC.
AB - We first report a multi-level-cell (MLC) spin-transfer torque memory (SPRAM) with series-connected magnetotunnel junctions (MTJs). The series MTJs (with different areas) show multi-level resistances by a combination of their magnetization directions. A four-level operation by spin-transfer-torque writing was experimentally demonstrated. A scheme for the write/read operation of the MLC SPRAM was also presented. Keywords: MRAM, SPRAM, spin, multi-bit, and MLC.
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U2 - 10.1109/VLSIT.2010.5556126
DO - 10.1109/VLSIT.2010.5556126
M3 - Conference contribution
AN - SCOPUS:77957864471
SN - 9781424476374
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 47
EP - 48
BT - 2010 Symposium on VLSI Technology, VLSIT 2010
T2 - 2010 Symposium on VLSI Technology, VLSIT 2010
Y2 - 15 June 2010 through 17 June 2010
ER -