A new compact SRAM cell by vertical MOSFET for low-power and stable operation

Hyoungjun Na; Tetsuo Endoh

doi:10.1109/IMW.2011.5873204

A new compact SRAM cell by vertical MOSFET for low-power and stable operation

Hyoungjun Na, Tetsuo Endoh

ENG - Electrical Engineering

Tohoku University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

In this paper, a compact SRAM cell with low-power and stable operation is proposed using vertical MOSFET technology, and its impact on the cell size and the performance is examined. Although the proposed SRAM cell is composed of 12 transistors, it has a small cell size, which is only 74% of the conventional 8T-SRAM cell, because of its stacked vertical MOSFET structure. The proposed SRAM cell with vertical MOSFET realizes a reduced power dissipation during the write operation which is 47% and 44% of the conventional 6T and 8TSRAM cell, respectively. Furthermore, the proposed SRAM cell with vertical MOSFET has achieved 3 times larger write and read Static Noise Margin (SNM) than that of the conventional planar 6T or 8T-SRAM cell, and its SNM is more tolerant against threshold voltage (Vth) fluctuation.

Original language	English
Title of host publication	2011 3rd IEEE International Memory Workshop, IMW 2011
DOIs	https://doi.org/10.1109/IMW.2011.5873204
Publication status	Published - 2011
Event	2011 3rd IEEE International Memory Workshop, IMW 2011 - Monterey, CA, United States Duration: 2011 May 22 → 2011 May 25

Publication series

Name	2011 3rd IEEE International Memory Workshop, IMW 2011

Conference

Conference	2011 3rd IEEE International Memory Workshop, IMW 2011
Country/Territory	United States
City	Monterey, CA
Period	11/5/22 → 11/5/25

Keywords

Cell Size
Low-power
SRAM
Stacked Vertical MOSFET
Static Noise Margin
Vertical MOSFET

Access to Document

10.1109/IMW.2011.5873204

Cite this

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title = "A new compact SRAM cell by vertical MOSFET for low-power and stable operation",

abstract = "In this paper, a compact SRAM cell with low-power and stable operation is proposed using vertical MOSFET technology, and its impact on the cell size and the performance is examined. Although the proposed SRAM cell is composed of 12 transistors, it has a small cell size, which is only 74% of the conventional 8T-SRAM cell, because of its stacked vertical MOSFET structure. The proposed SRAM cell with vertical MOSFET realizes a reduced power dissipation during the write operation which is 47% and 44% of the conventional 6T and 8TSRAM cell, respectively. Furthermore, the proposed SRAM cell with vertical MOSFET has achieved 3 times larger write and read Static Noise Margin (SNM) than that of the conventional planar 6T or 8T-SRAM cell, and its SNM is more tolerant against threshold voltage (Vth) fluctuation.",

keywords = "Cell Size, Low-power, SRAM, Stacked Vertical MOSFET, Static Noise Margin, Vertical MOSFET",

author = "Hyoungjun Na and Tetsuo Endoh",

year = "2011",

doi = "10.1109/IMW.2011.5873204",

language = "English",

isbn = "9781457702266",

series = "2011 3rd IEEE International Memory Workshop, IMW 2011",

booktitle = "2011 3rd IEEE International Memory Workshop, IMW 2011",

note = "2011 3rd IEEE International Memory Workshop, IMW 2011 ; Conference date: 22-05-2011 Through 25-05-2011",

}

TY - GEN

T1 - A new compact SRAM cell by vertical MOSFET for low-power and stable operation

AU - Na, Hyoungjun

AU - Endoh, Tetsuo

PY - 2011

Y1 - 2011

N2 - In this paper, a compact SRAM cell with low-power and stable operation is proposed using vertical MOSFET technology, and its impact on the cell size and the performance is examined. Although the proposed SRAM cell is composed of 12 transistors, it has a small cell size, which is only 74% of the conventional 8T-SRAM cell, because of its stacked vertical MOSFET structure. The proposed SRAM cell with vertical MOSFET realizes a reduced power dissipation during the write operation which is 47% and 44% of the conventional 6T and 8TSRAM cell, respectively. Furthermore, the proposed SRAM cell with vertical MOSFET has achieved 3 times larger write and read Static Noise Margin (SNM) than that of the conventional planar 6T or 8T-SRAM cell, and its SNM is more tolerant against threshold voltage (Vth) fluctuation.

AB - In this paper, a compact SRAM cell with low-power and stable operation is proposed using vertical MOSFET technology, and its impact on the cell size and the performance is examined. Although the proposed SRAM cell is composed of 12 transistors, it has a small cell size, which is only 74% of the conventional 8T-SRAM cell, because of its stacked vertical MOSFET structure. The proposed SRAM cell with vertical MOSFET realizes a reduced power dissipation during the write operation which is 47% and 44% of the conventional 6T and 8TSRAM cell, respectively. Furthermore, the proposed SRAM cell with vertical MOSFET has achieved 3 times larger write and read Static Noise Margin (SNM) than that of the conventional planar 6T or 8T-SRAM cell, and its SNM is more tolerant against threshold voltage (Vth) fluctuation.

KW - Cell Size

KW - Low-power

KW - SRAM

KW - Stacked Vertical MOSFET

KW - Static Noise Margin

KW - Vertical MOSFET

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U2 - 10.1109/IMW.2011.5873204

DO - 10.1109/IMW.2011.5873204

M3 - Conference contribution

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SN - 9781457702266

T3 - 2011 3rd IEEE International Memory Workshop, IMW 2011

BT - 2011 3rd IEEE International Memory Workshop, IMW 2011

T2 - 2011 3rd IEEE International Memory Workshop, IMW 2011

Y2 - 22 May 2011 through 25 May 2011

ER -

A new compact SRAM cell by vertical MOSFET for low-power and stable operation

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Keywords

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