In this paper, we present a new digital architecture of the neuron hardware that can be implemented using a field programmable gate array (FPGA). The proposed neuron applies a new Inverse Function Delayed Neuron model. In order to decrease the circuit area, we employ the stochastic logic. Because of the property of pseudo-analog operations of stochastic logic, the scale of a circuit is smaller than a conventional digital circuit. However, the stochastic logic requires the certain accumulation time for the more precise mean. Fortunately, the ID model of high-speed convergence remedies this shortcoming. The simulation experimental results show that the inverse function variance is related to the accumulation time, and this digital system can perform the associative memory.
|Journal||Midwest Symposium on Circuits and Systems|
|Publication status||Published - 2004|
|Event||The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan|
Duration: 2004 Jul 25 → 2004 Jul 28