A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique

K. Ota; K. Endo; Y. Okamoto; Y. Ando; H. Miyamoto; H. Shimawaki

doi:10.1109/IEDM.2009.5424398

A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique

K. Ota, K. Endo, Y. Okamoto, Y. Ando, H. Miyamoto, H. Shimawaki

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

58 Citations (Scopus)

Abstract

In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (V_th) uniformity and low on-resistance. In order to realize high V_th uniformity, a novel V_th control technique is proposed, which we call "piezo neutralization technique". This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess. Since the PNT layer neutralizes the polarization charges under the gate, the V _th comes to be independent of the gate-to-channel span. The fabricated normally-off GaN FET with PNT structure exhibits an excellent V _th uniformity (σ(V_th)=18 mV) and a state-of-the-art combination of the specific on-resistance (R_onA=500 mΩmm ²) and the breakdown voltage (V_B>1000 V). The normally-off GaN FETs wtih PNT structure show great promise as power devices.

Original language	English
Title of host publication	2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
Pages	7.3.1-7.3.4
DOIs	https://doi.org/10.1109/IEDM.2009.5424398
Publication status	Published - 2009 Dec 1
Externally published	Yes
Event	2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States Duration: 2009 Dec 7 → 2009 Dec 9

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2009 International Electron Devices Meeting, IEDM 2009
Country/Territory	United States
City	Baltimore, MD
Period	09/12/7 → 09/12/9

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.2009.5424398

Cite this

Ota, K., Endo, K., Okamoto, Y., Ando, Y., Miyamoto, H., & Shimawaki, H. (2009). A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest (pp. 7.3.1-7.3.4). [5424398] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2009.5424398

A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique. / Ota, K.; Endo, K.; Okamoto, Y. et al.
2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. p. 7.3.1-7.3.4 5424398 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ota, K, Endo, K, Okamoto, Y, Ando, Y, Miyamoto, H & Shimawaki, H 2009, A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique. in 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest., 5424398, Technical Digest - International Electron Devices Meeting, IEDM, pp. 7.3.1-7.3.4, 2009 International Electron Devices Meeting, IEDM 2009, Baltimore, MD, United States, 09/12/7. https://doi.org/10.1109/IEDM.2009.5424398

Ota K, Endo K, Okamoto Y, Ando Y, Miyamoto H, Shimawaki H. A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. p. 7.3.1-7.3.4. 5424398. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2009.5424398

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title = "A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique",

abstract = "In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (Vth) uniformity and low on-resistance. In order to realize high Vth uniformity, a novel Vth control technique is proposed, which we call {"}piezo neutralization technique{"}. This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess. Since the PNT layer neutralizes the polarization charges under the gate, the V th comes to be independent of the gate-to-channel span. The fabricated normally-off GaN FET with PNT structure exhibits an excellent V th uniformity (σ(Vth)=18 mV) and a state-of-the-art combination of the specific on-resistance (RonA=500 mΩmm 2) and the breakdown voltage (VB>1000 V). The normally-off GaN FETs wtih PNT structure show great promise as power devices.",

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AU - Shimawaki, H.

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N2 - In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (Vth) uniformity and low on-resistance. In order to realize high Vth uniformity, a novel Vth control technique is proposed, which we call "piezo neutralization technique". This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess. Since the PNT layer neutralizes the polarization charges under the gate, the V th comes to be independent of the gate-to-channel span. The fabricated normally-off GaN FET with PNT structure exhibits an excellent V th uniformity (σ(Vth)=18 mV) and a state-of-the-art combination of the specific on-resistance (RonA=500 mΩmm 2) and the breakdown voltage (VB>1000 V). The normally-off GaN FETs wtih PNT structure show great promise as power devices.

AB - In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (Vth) uniformity and low on-resistance. In order to realize high Vth uniformity, a novel Vth control technique is proposed, which we call "piezo neutralization technique". This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess. Since the PNT layer neutralizes the polarization charges under the gate, the V th comes to be independent of the gate-to-channel span. The fabricated normally-off GaN FET with PNT structure exhibits an excellent V th uniformity (σ(Vth)=18 mV) and a state-of-the-art combination of the specific on-resistance (RonA=500 mΩmm 2) and the breakdown voltage (VB>1000 V). The normally-off GaN FETs wtih PNT structure show great promise as power devices.

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A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique

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