A novel delayed flip-flop circuit using resonant tunneling logic gates

Koichi Maezawa; Hideaki Matsuzaki; Tomoyuki Akeyoshi; Jiro Osaka; Masafumi Yamamoto; Taiichi Otsuji

doi:10.1143/JJAP.37.L212

A novel delayed flip-flop circuit using resonant tunneling logic gates

Koichi Maezawa, Hideaki Matsuzaki, Tomoyuki Akeyoshi, Jiro Osaka, Masafumi Yamamoto, Taiichi Otsuji

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Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

A novel delayed flip-flop circuit using monostable-bistable transition logic elements (MOBILEs) was proposed, and was fabricated using resonant-tunneling-diode/high-electron-mobility-transistor integration technology on an InP substrate. Error free operations at up to 12.5 Gb/s were demonstrated at room temperature.

Original language	English
Pages (from-to)	L212-L213
Journal	Japanese Journal of Applied Physics
Volume	37
Issue number	2 SUPPL. B
DOIs	https://doi.org/10.1143/JJAP.37.L212
Publication status	Published - 1998 Feb 15

Keywords

Delayed flip-flop
HEMT
InAlAs
InGaAs
InP
Resonant tunneling diode

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10.1143/JJAP.37.L212

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abstract = "A novel delayed flip-flop circuit using monostable-bistable transition logic elements (MOBILEs) was proposed, and was fabricated using resonant-tunneling-diode/high-electron-mobility-transistor integration technology on an InP substrate. Error free operations at up to 12.5 Gb/s were demonstrated at room temperature.",

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AU - Matsuzaki, Hideaki

AU - Akeyoshi, Tomoyuki

AU - Osaka, Jiro

AU - Yamamoto, Masafumi

AU - Otsuji, Taiichi

PY - 1998/2/15

Y1 - 1998/2/15

N2 - A novel delayed flip-flop circuit using monostable-bistable transition logic elements (MOBILEs) was proposed, and was fabricated using resonant-tunneling-diode/high-electron-mobility-transistor integration technology on an InP substrate. Error free operations at up to 12.5 Gb/s were demonstrated at room temperature.

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KW - Delayed flip-flop

KW - HEMT

KW - InAlAs

KW - InGaAs

KW - InP

KW - Resonant tunneling diode

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JF - Japanese Journal of Applied Physics

IS - 2 SUPPL. B

ER -

A novel delayed flip-flop circuit using resonant tunneling logic gates

Abstract

Keywords

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