A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

M. Sekikawa; K. Kiyoyama; H. Hasegawa; K. Miura; T. Fukushima; S. Ikeda; T. Tanaka; H. Ohno; M. Koyanagi

doi:10.1109/IEDM.2008.4796645

A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

M. Sekikawa, K. Kiyoyama, H. Hasegawa, K. Miura, T. Fukushima, S. Ikeda, T. Tanaka, H. Ohno, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Citations (Scopus)

Abstract

A novel reconfigurable logic block with SPRAM (SPin-transfer torque RAM) is demonstrated. Magnetic elements of 50 × 200 nm ² in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kω (parallel) and the MR ratio is 91.7 %.

Original language	English
Title of host publication	2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs	https://doi.org/10.1109/IEDM.2008.4796645
Publication status	Published - 2008
Event	2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States Duration: 2008 Dec 15 → 2008 Dec 17

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2008 IEEE International Electron Devices Meeting, IEDM 2008
Country/Territory	United States
City	San Francisco, CA
Period	08/12/15 → 08/12/17

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10.1109/IEDM.2008.4796645

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Sekikawa, M., Kiyoyama, K., Hasegawa, H., Miura, K., Fukushima, T., Ikeda, S., Tanaka, T., Ohno, H., & Koyanagi, M. (2008). A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor. In 2008 IEEE International Electron Devices Meeting, IEDM 2008 Article 4796645 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2008.4796645

@inproceedings{3e85d7d5c2324abd9fb7d8f4bb3f84a2,

title = "A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor",

abstract = "A novel reconfigurable logic block with SPRAM (SPin-transfer torque RAM) is demonstrated. Magnetic elements of 50 × 200 nm 2 in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kω (parallel) and the MR ratio is 91.7 %.",

author = "M. Sekikawa and K. Kiyoyama and H. Hasegawa and K. Miura and T. Fukushima and S. Ikeda and T. Tanaka and H. Ohno and M. Koyanagi",

year = "2008",

doi = "10.1109/IEDM.2008.4796645",

language = "English",

isbn = "9781424423781",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

booktitle = "2008 IEEE International Electron Devices Meeting, IEDM 2008",

note = "2008 IEEE International Electron Devices Meeting, IEDM 2008 ; Conference date: 15-12-2008 Through 17-12-2008",

}

Sekikawa, M, Kiyoyama, K, Hasegawa, H, Miura, K, Fukushima, T , Ikeda, S , Tanaka, T , Ohno, H & Koyanagi, M 2008, A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor. in 2008 IEEE International Electron Devices Meeting, IEDM 2008., 4796645, Technical Digest - International Electron Devices Meeting, IEDM, 2008 IEEE International Electron Devices Meeting, IEDM 2008, San Francisco, CA, United States, 08/12/15. https://doi.org/10.1109/IEDM.2008.4796645

A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor. / Sekikawa, M.; Kiyoyama, K.; Hasegawa, H. et al.
2008 IEEE International Electron Devices Meeting, IEDM 2008. 2008. 4796645 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

AU - Sekikawa, M.

AU - Kiyoyama, K.

AU - Hasegawa, H.

AU - Miura, K.

AU - Fukushima, T.

AU - Ikeda, S.

AU - Tanaka, T.

AU - Ohno, H.

AU - Koyanagi, M.

PY - 2008

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AB - A novel reconfigurable logic block with SPRAM (SPin-transfer torque RAM) is demonstrated. Magnetic elements of 50 × 200 nm 2 in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kω (parallel) and the MR ratio is 91.7 %.

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M3 - Conference contribution

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T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2008 IEEE International Electron Devices Meeting, IEDM 2008

T2 - 2008 IEEE International Electron Devices Meeting, IEDM 2008

Y2 - 15 December 2008 through 17 December 2008

ER -

A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

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