Abstract
In this paper, we present an efficient countermeasure against fault sensitivity analysis (FSA) based on configurable delay blocks (CDBs). FSA is a new type of fault attack, which exploits the relationship between fault sensitivity (FS) and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against differential fault analysis (DFA), such as redundancy calculation, masked and-or, and wave dynamic differential logic. The proposed countermeasure can thwart both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li's countermeasure concept that removes the dependency between FSs and secret data. The postmanufacture configuration of the CDBs allows minimization of the overhead in operating frequency that comes from manufacture variability. In this paper, we also present an implementation of the proposed countermeasure in application-specified integrated circuit, and describe its configuration method. We then investigate the hardware overhead of the proposed countermeasure for an advanced encryption standard processor and demonstrate its validity through an experiment.
Original language | English |
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Article number | 6872596 |
Pages (from-to) | 1429-1438 |
Number of pages | 10 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 23 |
Issue number | 8 |
DOIs | |
Publication status | Published - 2015 Aug 1 |
Keywords
- Advanced encryption standard (AES)
- application-specified integrated circuit (ASIC) implementation
- fault sensitivity analysis (FSA)
- side-channel analysis
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering