A study of nondestructive inspection method of bump connection in three dimensionally stacked chip structures

The three dimensionally stacked chip structures of electronic packages and modules have started to be used to maximize assembly density and to minimize signal delay. Since the thickness of the stacked silicon chips has been thinned to less than 100 pim, the local thermal deformation of chips has increased drastically because of the decrease of bending elasticity of the chips. In such a stacked structure, it is hard to inspect the adhesion condition of metallic bumps that connect a bottom chip with an upper chip. We have, therefore, proposed a new nondestructive evaluation method for detecting delamination between a chip and metallic bumps by applying a measurement of local surface deformation of the chip. The magnitude of the local deformation was calculated using a three-dimensional finite element analysis. The local deformation of a silicon chip between the nearest two bumps is a strong function of the thickness of the chip, the pitch of the bumps, and the magnitude of the mismatch of the thermal expansion coefficient between the bump and underfill material. The amplitude of the local deformation exceeds 200 nm easily, and it sometimes reaches 600 nm when the underfill material used for assembly was assumed to be epoxy resin. To confirm that such an estimated local deformation of an LSI chip thinner than 100 ptm appears in actual stacked structures, we applied a scanning blue laser microscope to measure the local deformation. The measured local deformation was about 200 nm when the thickness of a chip was 100 ptm, as was predicted by a finite element analysis. In addition, the surface deformation of the upper chip changed drastically depending on the layout of the metallic bumps between the upper and the lower chip. The predicted local displacement at the sample surface was also validated by using a white light interference microscope.