TY - GEN
T1 - A Study on Evaluation of Interface Defect Density on High-K/SiO2/Si and SiO2/Si Gate Stacks using Scanning Nonlinear Dielectric Microscopy
AU - Suzuki, Koharu
AU - Yamasue, Kohei
AU - Cho, Yasuo
N1 - Funding Information:
ACKNOWLEDGMENT This work is partly supported by a Grant-in-Aid for Scientific Research (16H02330) from the Japan Society for the Promotion of Science.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - We discuss the feasibility of interface defect density estimation using scanning nonlinear dielectric microscopy (SNDM). With reference to the previous results on SiO2/SiC gate stacks, we evaluate the non-uniformity in the microscopy images of SiO2/Si and high-κ/SiO2/Si gate stacks. The results suggest that a high-κ layer on a SiO2/Si gate stack has little impact on the quality of interface. Our procedure possibly gives a useful method for the nanoscale evaluation of interface quality at gate stacks with Si substrates. We also measure local capacitance voltage (CV) spectrum by newly developed time-resolved SNDM, which show CV spectrum gradually changed during the measurement.
AB - We discuss the feasibility of interface defect density estimation using scanning nonlinear dielectric microscopy (SNDM). With reference to the previous results on SiO2/SiC gate stacks, we evaluate the non-uniformity in the microscopy images of SiO2/Si and high-κ/SiO2/Si gate stacks. The results suggest that a high-κ layer on a SiO2/Si gate stack has little impact on the quality of interface. Our procedure possibly gives a useful method for the nanoscale evaluation of interface quality at gate stacks with Si substrates. We also measure local capacitance voltage (CV) spectrum by newly developed time-resolved SNDM, which show CV spectrum gradually changed during the measurement.
KW - high-k bias temperature instability
KW - Scanning nonlinear dielectric microscopy (SNDM)
KW - SiO/Si
UR - http://www.scopus.com/inward/record.url?scp=85080092175&partnerID=8YFLogxK
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U2 - 10.1109/IIRW47491.2019.8989881
DO - 10.1109/IIRW47491.2019.8989881
M3 - Conference contribution
AN - SCOPUS:85080092175
T3 - IEEE International Integrated Reliability Workshop Final Report
BT - 2019 IEEE International Integrated Reliability Workshop, IIRW 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Integrated Reliability Workshop, IIRW 2019
Y2 - 13 October 2019 through 17 October 2019
ER -