A Sub-10-ns 16 × 16 Multiplier Using 0.6-µm CMOS Technology

Yukihito Oowaki, Kenji Numata, Kenji Tsuchiya, Kazushi Tsuda, Hiroshi Takato, Naoko Takenouchi, Akihiro Nitayama, Shigeyoshi Watanabe, Takayuki Kobayashi, Masahiko Chiba, Akimichi Hojo, Kazunori Ohuchi

Research output: Contribution to journalArticlepeer-review

19 Citations (Scopus)


A 16×16-bit parallel multiplier fabricated in a 0.6- µm CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-µm CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.

Original languageEnglish
Pages (from-to)762-767
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number5
Publication statusPublished - 1987 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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