A Sub-10-ns 16 × 16 Multiplier Using 0.6-µm CMOS Technology

Yukihito Oowaki; Kenji Numata; Kenji Tsuchiya; Kazushi Tsuda; Hiroshi Takato; Naoko Takenouchi; Akihiro Nitayama; Shigeyoshi Watanabe; Takayuki Kobayashi; Masahiko Chiba; Akimichi Hojo; Kazunori Ohuchi

doi:10.1109/JSSC.1987.1052811

A Sub-10-ns 16 × 16 Multiplier Using 0.6-µm CMOS Technology

Yukihito Oowaki, Kenji Numata, Kenji Tsuchiya, Kazushi Tsuda, Hiroshi Takato, Naoko Takenouchi, Akihiro Nitayama, Shigeyoshi Watanabe, Takayuki Kobayashi, Masahiko Chiba, Akimichi Hojo, Kazunori Ohuchi

Research output: Contribution to journal › Article › peer-review

19 Citations (Scopus)

Abstract

A 16×16-bit parallel multiplier fabricated in a 0.6- µm CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-µm CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.

Original language	English
Pages (from-to)	762-767
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	22
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.1987.1052811
Publication status	Published - 1987 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.1987.1052811

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title = "A Sub-10-ns 16 × 16 Multiplier Using 0.6-µm CMOS Technology",

abstract = "A 16×16-bit parallel multiplier fabricated in a 0.6- µm CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-µm CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.",

author = "Yukihito Oowaki and Kenji Numata and Kenji Tsuchiya and Kazushi Tsuda and Hiroshi Takato and Naoko Takenouchi and Akihiro Nitayama and Shigeyoshi Watanabe and Takayuki Kobayashi and Masahiko Chiba and Akimichi Hojo and Kazunori Ohuchi",

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T1 - A Sub-10-ns 16 × 16 Multiplier Using 0.6-µm CMOS Technology

AU - Oowaki, Yukihito

AU - Numata, Kenji

AU - Tsuchiya, Kenji

AU - Tsuda, Kazushi

AU - Takato, Hiroshi

AU - Takenouchi, Naoko

AU - Nitayama, Akihiro

AU - Watanabe, Shigeyoshi

AU - Kobayashi, Takayuki

AU - Chiba, Masahiko

AU - Hojo, Akimichi

AU - Ohuchi, Kazunori

PY - 1987/10

Y1 - 1987/10

N2 - A 16×16-bit parallel multiplier fabricated in a 0.6- µm CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-µm CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.

AB - A 16×16-bit parallel multiplier fabricated in a 0.6- µm CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-µm CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.

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A Sub-10-ns 16 × 16 Multiplier Using 0.6-µm CMOS Technology

Abstract

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