TY - GEN
T1 - A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery
AU - Onizawa, Naoya
AU - Mochizuki, Akira
AU - Tamakoshi, Akira
AU - Hanyu, Takahiro
PY - 2015/8/5
Y1 - 2015/8/5
N2 - In energy harvesting applications, a power supply generated from a renewable power source is unstable that may induce a sudden power outage, losing data being processed. This paper introduces a sudden power-outage resilient nonvolatile microprocessor based on a flashback architecture for immediate system recovery, where nonvolatile storage elements, called magnetic-tunnel-junction (MTJ), are exploited with standard CMOS gates. In the proposed architecture, data stored within a past few clocks are also kept in redundant MTJ-based nonvolatile flip-flops (NV-FF), while storing the current data in NV-FFs. Even if a sudden outage induces a failure of storing the data partly, the inconsistency of the stored data is automatically and immediately recovered by reordering the past data, which enables a continuous operation. A nonvolatile Cortex-M0 processor based on the proposed architecture is implemented using 90nm CMOS/100nm MTJ technologies. It demonstrates the immediate system recovery after a sudden power outage with a 32% area reduction compared to a triple modular redundancy based equivalent microprocessor.
AB - In energy harvesting applications, a power supply generated from a renewable power source is unstable that may induce a sudden power outage, losing data being processed. This paper introduces a sudden power-outage resilient nonvolatile microprocessor based on a flashback architecture for immediate system recovery, where nonvolatile storage elements, called magnetic-tunnel-junction (MTJ), are exploited with standard CMOS gates. In the proposed architecture, data stored within a past few clocks are also kept in redundant MTJ-based nonvolatile flip-flops (NV-FF), while storing the current data in NV-FFs. Even if a sudden outage induces a failure of storing the data partly, the inconsistency of the stored data is automatically and immediately recovered by reordering the past data, which enables a continuous operation. A nonvolatile Cortex-M0 processor based on the proposed architecture is implemented using 90nm CMOS/100nm MTJ technologies. It demonstrates the immediate system recovery after a sudden power outage with a 32% area reduction compared to a triple modular redundancy based equivalent microprocessor.
UR - http://www.scopus.com/inward/record.url?scp=84949549486&partnerID=8YFLogxK
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U2 - 10.1109/NANOARCH.2015.7180584
DO - 10.1109/NANOARCH.2015.7180584
M3 - Conference contribution
AN - SCOPUS:84949549486
T3 - Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015
SP - 39
EP - 44
BT - Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015
Y2 - 8 July 2015 through 10 July 2015
ER -
