A systematic approach for analyzing fast addition algorithms using counter tree diagrams

Naofumi Homma, Jun Sakiyama, Taihei Wakamatsu, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalConference articlepeer-review

7 Citations (Scopus)


This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. In this paper, we focus on an application of CTDs to the analysis of two-operand RB adders with limited carry propagation. The analysis result shows that there exists possible two types of 3-stage CTDs for the RB adders. From this result, we can confirm that well-known RB adders are classified into one of the two types.

Original languageEnglish
Pages (from-to)V-197-V-200
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2004 Sept 6
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 2004 May 232004 May 26

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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