TY - GEN
T1 - A test circuit for extremely low gate leakage current measurement of 10 aA for 80,000 MOSFETs in 80 s
AU - Kumagai, Y.
AU - Inatsuka, T.
AU - Kuroda, R.
AU - Teramoto, A.
AU - Suwa, T.
AU - Sugawa, S.
AU - Ohmi, T.
PY - 2012
Y1 - 2012
N2 - We propose a test circuit which can evaluate statistical characteristics of gate leakage current in a very short time with high accuracy (10 17 - 10 17 A, 87344 samples in 80 s). The absolute value of the gate leakage current is verified and the repeatability error is 110 18 A. Using the test circuit, random telegraph signal of the gate leakage current and stress induced leakage current are evaluated statistically.
AB - We propose a test circuit which can evaluate statistical characteristics of gate leakage current in a very short time with high accuracy (10 17 - 10 17 A, 87344 samples in 80 s). The absolute value of the gate leakage current is verified and the repeatability error is 110 18 A. Using the test circuit, random telegraph signal of the gate leakage current and stress induced leakage current are evaluated statistically.
UR - http://www.scopus.com/inward/record.url?scp=84862092704&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84862092704&partnerID=8YFLogxK
U2 - 10.1109/ICMTS.2012.6190631
DO - 10.1109/ICMTS.2012.6190631
M3 - Conference contribution
AN - SCOPUS:84862092704
SN - 9781467310284
T3 - IEEE International Conference on Microelectronic Test Structures
SP - 131
EP - 136
BT - ICMTS 2012 - 2012 IEEE International Conference on Microelectronic Test Structures
T2 - 2012 IEEE International Conference on Microelectronic Test Structures, ICMTS 2012
Y2 - 20 March 2012 through 22 March 2012
ER -