TY - GEN
T1 - A unique and accurate extraction technique of the asymmetric bottom-pillar resistance for the vertical MOSFET
AU - Sakui, Koji
AU - Endoh, Tetsuo
PY - 2010/6/29
Y1 - 2010/6/29
N2 - The concept of the measurement technique is to separate the paths by at least two directions; one is the current path, where the drain current flows, and the other is the noncurrent path, where the voltage is measured with the connection to the high-Z gate of the monitor circuit. The proposed measurement technique has been validated by HSPICE simulation.
AB - The concept of the measurement technique is to separate the paths by at least two directions; one is the current path, where the drain current flows, and the other is the noncurrent path, where the voltage is measured with the connection to the high-Z gate of the monitor circuit. The proposed measurement technique has been validated by HSPICE simulation.
UR - http://www.scopus.com/inward/record.url?scp=77953904532&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77953904532&partnerID=8YFLogxK
U2 - 10.1109/ICMTS.2010.5466812
DO - 10.1109/ICMTS.2010.5466812
M3 - Conference contribution
AN - SCOPUS:77953904532
SN - 9781424469154
T3 - IEEE International Conference on Microelectronic Test Structures
SP - 220
EP - 224
BT - 2010 International Conference on Microelectronic Test Structures, 23rd IEEE ICMTS Conference Proceedings
T2 - 2010 International Conference on Microelectronic Test Structures, ICMTS 2010
Y2 - 22 March 2010 through 25 March 2010
ER -