In this paper, a tailbitlng block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is Increased. Instead of the SW, we combined the tailbltlng method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.