A WiMAX turbo decoder with tailbiting BIP architecture

Hiroaki Arai; Naoto Miyamoto; Koji Kotani; Hisanori Fujisawa; Takashi Ito

doi:10.1109/ASSCC.2009.5357175

A WiMAX turbo decoder with tailbiting BIP architecture

Hiroaki Arai, Naoto Miyamoto, Koji Kotani, Hisanori Fujisawa, Takashi Ito

FRIS - Advanced Interdisciplinary Research Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

In this paper, a tailbitlng block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is Increased. Instead of the SW, we combined the tailbltlng method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm² using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

Original language	English
Title of host publication	Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages	377-380
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2009.5357175
Publication status	Published - 2009
Event	2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan, Province of China Duration: 2009 Nov 16 → 2009 Nov 18

Publication series

Name	Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Conference

Conference	2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Country/Territory	Taiwan, Province of China
City	Taipei
Period	09/11/16 → 09/11/18

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10.1109/ASSCC.2009.5357175

Cite this

Arai, H., Miyamoto, N., Kotani, K., Fujisawa, H., & Ito, T. (2009). A WiMAX turbo decoder with tailbiting BIP architecture. In Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 (pp. 377-380). Article 5357175 (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009). https://doi.org/10.1109/ASSCC.2009.5357175

@inproceedings{c0f2ea9c82c9461baf89ea573eedaaad,

title = "A WiMAX turbo decoder with tailbiting BIP architecture",

abstract = "In this paper, a tailbitlng block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is Increased. Instead of the SW, we combined the tailbltlng method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.",

author = "Hiroaki Arai and Naoto Miyamoto and Koji Kotani and Hisanori Fujisawa and Takashi Ito",

year = "2009",

doi = "10.1109/ASSCC.2009.5357175",

language = "English",

isbn = "9781424444342",

series = "Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009",

pages = "377--380",

booktitle = "Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009",

note = "2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 ; Conference date: 16-11-2009 Through 18-11-2009",

}

Arai, H, Miyamoto, N, Kotani, K, Fujisawa, H & Ito, T 2009, A WiMAX turbo decoder with tailbiting BIP architecture. in Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009., 5357175, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, pp. 377-380, 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009, Taipei, Taiwan, Province of China, 09/11/16. https://doi.org/10.1109/ASSCC.2009.5357175

A WiMAX turbo decoder with tailbiting BIP architecture. / Arai, Hiroaki; Miyamoto, Naoto; Kotani, Koji et al.
Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. 2009. p. 377-380 5357175 (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A WiMAX turbo decoder with tailbiting BIP architecture

AU - Arai, Hiroaki

AU - Miyamoto, Naoto

AU - Kotani, Koji

AU - Fujisawa, Hisanori

AU - Ito, Takashi

PY - 2009

Y1 - 2009

N2 - In this paper, a tailbitlng block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is Increased. Instead of the SW, we combined the tailbltlng method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

AB - In this paper, a tailbitlng block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large memory size when the number of pipeline stages is Increased. Instead of the SW, we combined the tailbltlng method with BIP. Consequently, more than 50% of the warm-up calculation was reduced, and necessary memory size became constant. We have implemented a tailbiting BIP WiMAX turbo decoder with 4 pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieves 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

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T3 - Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

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BT - Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

T2 - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Y2 - 16 November 2009 through 18 November 2009

ER -

A WiMAX turbo decoder with tailbiting BIP architecture

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