TY - GEN
T1 - A WiMAX turbo decoder with tailbiting BIP architecture
AU - Arai, Hiroaki
AU - Miyamoto, Naoto
AU - Kotani, Koji
AU - Fujisawa, Hisanori
AU - Ito, Takashi
PY - 2010
Y1 - 2010
N2 - A tailbiting block-interleaved pipelining (TB-BIP) is proposed for deeply-pipelined turbo decoders. Conventional sliding window block-interleaved pipelining (SW-BIP) turbo decoders suffer from many warm-up calculations when the number of pipeline stages is increased. However, by using TB-BIP, more than 50% of the warm-up calculations are reduced as compared to SW-BIP. We have implemented a TB-BIP WiMAX turbo decoder with four pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieved 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.
AB - A tailbiting block-interleaved pipelining (TB-BIP) is proposed for deeply-pipelined turbo decoders. Conventional sliding window block-interleaved pipelining (SW-BIP) turbo decoders suffer from many warm-up calculations when the number of pipeline stages is increased. However, by using TB-BIP, more than 50% of the warm-up calculations are reduced as compared to SW-BIP. We have implemented a TB-BIP WiMAX turbo decoder with four pipeline stages in the area of 3.8 mm2 using a 0.18 μm CMOS technology. The chip achieved 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.
UR - http://www.scopus.com/inward/record.url?scp=77951240345&partnerID=8YFLogxK
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U2 - 10.1109/ASPDAC.2010.5419858
DO - 10.1109/ASPDAC.2010.5419858
M3 - Conference contribution
AN - SCOPUS:77951240345
SN - 9781424457656
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 371
EP - 372
BT - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
T2 - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Y2 - 18 January 2010 through 21 January 2010
ER -