@inproceedings{bef547f0e2d74532a83a94cfe164dcf6,
title = "Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system",
abstract = "A novel memory test system is needed for future STTMRAM mass production that supports error bit analysis and its mode categorization on STT-MRAM chip measurement, as STTMRAM cell's switching is a probabilistic phenomenon based on quantum mechanics. In order to meet this requirement, we successfully developed a novel current measurement module on gigabit class memory test system that can measure the time domain switching current of each bit with nanosecond and microampere resolution. Moreover, we demonstrated the world's first results that our developed memory test system detects all error bits in fabricated STT-MRAM chip and categorizes error bit mode according to the switching characteristics of each error bit. This novel memory test system with the function of accurate and high speed time domain current measurement on the same level as single bit measurement equipment is expected to accelerate RD and mass production of STT-MRAM and other applications such as ReRAM and PCM.",
keywords = "error bit analysis, error bit mode, memory test system, STT-MRAM, switching current;",
author = "R. Tamura and I. Mori and N. Watanabe and H. Koike and T. Endoh",
note = "Funding Information: ACKNOWLEDGMENT This work was supported in part by CIES's Industrial Affiliation on the STT MRAM program and JST-OPERA (PI Tetsuo Endoh). Publisher Copyright: {\textcopyright} 2018 IEEE.; 18th Non-Volatile Memory Technology Symposium, NVMTS 2018 ; Conference date: 22-10-2018 Through 24-10-2018",
year = "2019",
month = jan,
day = "4",
doi = "10.1109/NVMTS.2018.8603113",
language = "English",
series = "NVMTS 2018 - Non-Volatile Memory Technology Symposium 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "NVMTS 2018 - Non-Volatile Memory Technology Symposium 2018",
address = "United States",
}