Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

A. Rothschild, X. Shi, J. L. Everaert, C. Kerner, T. Chiarella, T. Hoffmann, C. Vrancken, A. Shickova, H. Yoshinao, R. Mitsuhashi, M. Niwa, A. Lauwers, A. Veloso, J. Kittl, P. Absil, S. Biesemans

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)


We achieved 635/250μA/μm@Ioff=20pA/μm unstrained FuSI/HfSiON nMOS/pMOS devices (Vdd=1.1V, Ioff=20pA/μm, Jg=20/8 mA/cm2) representing a 20%/2% device improvement enabling 10% power delay improvement compared to our previous report [1]. This was reached by a careful optimization of the nitrogen content into our HfSiON gate dielectric (to be 3-6%). Second, we demonstrate that the nitrogen content impacts not only the device performance but also the gate leakage current, the gate oxide integrity as well as PBTI and NBTI. We also report for the first time a 0.8 nm EOT HfSiON dielectric with Ni-FuSI gate and its impact on ring oscillator delay resulting in 9ps delays. This is an absolute record for any CMOS with metal gate to date.

Original languageEnglish
Article number4339691
Pages (from-to)198-199
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2007
Externally publishedYes
Event2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
Duration: 2007 Jun 122007 Jun 14

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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