Advanced FinFET process technology for 20 nm node and beyond

M. Masahara, T. Matsukawa, K. Endo, Y. X. Liu, W. Mizubayashi, S. Migita, S. O'Uchi, H. Ota, Y. Morita

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Citations (Scopus)


One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a catastrophic increase in power dissipation of the circuit due to short channel effects (SCEs). Fortunately, double-gate FinFETs have a promising potential to overcome this issue due to their superior SCE immunity even with an undoped channel thanks to the 3D structure. This paper presents novel FinFET process technologies for 20 nm node and beyond.

Original languageEnglish
Title of host publication4th IEEE International NanoElectronics Conference, INEC 2011
Publication statusPublished - 2011
Event4th IEEE International Nanoelectronics Conference, INEC 2011 - Tao-Yuan, Taiwan, Province of China
Duration: 2011 Jun 212011 Jun 24

Publication series

NameProceedings - International NanoElectronics Conference, INEC
ISSN (Print)2159-3523


Conference4th IEEE International Nanoelectronics Conference, INEC 2011
Country/TerritoryTaiwan, Province of China


  • FinFET
  • Metal Gate
  • Metal S/D
  • NiSi
  • Wet Etching


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